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[PATCH v2 2/9] x86: slightly rearrange struct insn_template
- From: Jan Beulich <jbeulich at suse dot com>
- To: "binutils at sourceware dot org" <binutils at sourceware dot org>
- Cc: "H.J. Lu" <hjl dot tools at gmail dot com>
- Date: Mon, 28 Oct 2019 09:03:25 +0100
- Subject: [PATCH v2 2/9] x86: slightly rearrange struct insn_template
- References: <b53b0a7a-781c-e705-82a1-3680bf635cbc@suse.com>
This avoids holes between the individual fields, (potentially) shrinking
the overall template table size by 4 bytes per entry.
opcodes/
2019-10-XX Jan Beulich <jbeulich@suse.com>
* i386-gen.c (output_i386_opcode): Change order of fields
emitted to output.
* i386-opc.h (struct insn_template): Move operands field.
Convert extension_opcode field to unsigned short.
* i386-tbl.h: Re-generate.
---
v2: New.
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -1294,8 +1294,7 @@ output_i386_opcode (FILE *table, const c
}
fprintf (table, " { \"%s\", %s, %s, %s, %s,\n",
- name, operands, base_opcode, extension_opcode,
- opcode_length);
+ name, base_opcode, extension_opcode, opcode_length, operands);
process_i386_cpu_flag (table, cpu_flags, 0, ",", " ", lineno);
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -852,9 +852,6 @@ typedef struct insn_template
/* instruction name sans width suffix ("mov" for movl insns) */
char *name;
- /* how many operands */
- unsigned int operands;
-
/* base_opcode is the fundamental opcode byte without optional
prefix(es). */
unsigned int base_opcode;
@@ -871,12 +868,15 @@ typedef struct insn_template
AMD 3DNow! instructions.
If this template has no extension opcode (the usual case) use None
Instructions */
- unsigned int extension_opcode;
+ unsigned short extension_opcode;
#define None 0xffff /* If no extension_opcode is possible. */
/* Opcode length. */
unsigned char opcode_length;
+ /* how many operands */
+ unsigned char operands;
+
/* cpu feature flags */
i386_cpu_flags cpu_flags;