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[PATCH, BINUTILS, AArch64, 1/3] Remove ldgv and stgv instructions from Armv8.5-A Memory Tagging Extension.
- From: Kyrill Tkachov <kyrylo dot tkachov at foss dot arm dot com>
- To: "binutils at sourceware dot org" <binutils at sourceware dot org>
- Cc: Sudi Das <Sudi dot Das at arm dot com>, "nickc at redhat dot com" <nickc at redhat dot com>
- Date: Fri, 25 Jan 2019 09:33:45 +0000
- Subject: [PATCH, BINUTILS, AArch64, 1/3] Remove ldgv and stgv instructions from Armv8.5-A Memory Tagging Extension.
Hi
This patch is part of a series of patches to introduce a few changes to the
Armv8.5-A Memory Tagging Extension. This patch removes the LDGV and STGV
instructions. These instructions needed special infrastructure to support
[base]! style for addressing mode. That is also removed now.
For ease of review I have not added the regenerated files in the patch. I
will add those in my final commit.
Builds and reg tests all pass on aarch64-none-elf.
Is this ok for trunk?
Thanks
Sudi
*** gas/ChangeLog ***
2019-01-25 Sudakshina Das <sudi.das@arm.com>
Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
* config/tc-aarch64.c (parse_address_main): Remove support for
[base]! address expression.
(parse_operands): Remove support for AARCH64_OPND_ADDR_SIMPLE_2.
(warn_unpredictable_ldst): Remove support for ldstgv_indexed.
* testsuite/gas/aarch64/armv8_5-a-memtag.d: Remove tests for ldgv
and stgv.
* testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise.
* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
* testsuite/gas/aarch64/illegal-memtag.s: Likewise.
*** include/ChangeLog ***
2019-01-25 Sudakshina Das <sudi.das@arm.com>
Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): Remove
AARCH64_OPND_ADDR_SIMPLE_2.
(enum aarch64_insn_class): Remove ldstgv_indexed.
*** opcodes/ChangeLog ***
2019-01-25 Sudakshina Das <sudi.das@arm.com>
Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
* aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
* aarch64-asm.h (ins_addr_simple_2): Likeiwse.
* aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
* aarch64-dis.h (ext_addr_simple_2): Likewise.
* aarch64-opc.c (operand_general_constraint_met_p): Remove
case for ldstgv_indexed.
(aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
* aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
(AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 461c39b104365bc1cc77789a1f787e8da9ee0c92..537f00ceb271872316c86317153097cecb5dec20 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -3381,7 +3381,6 @@ parse_shifter_operand_reloc (char **str, aarch64_opnd_info *operand,
[base,Wm,(S|U)XTW {#imm}]
Pre-indexed
[base,#imm]!
- [base]! // in ld/stgv
Post-indexed
[base],#imm
[base],Xm // in SIMD ld/st structure
@@ -3690,11 +3689,10 @@ parse_address_main (char **str, aarch64_opnd_info *operand,
}
/* If at this point neither .preind nor .postind is set, we have a
- bare [Rn]{!}; reject [Rn]! except for ld/stgv but accept [Rn]
- as a shorthand for [Rn,#0]. */
+ bare [Rn]{!}; reject [Rn]! accept [Rn] as a shorthand for [Rn,#0]. */
if (operand->addr.preind == 0 && operand->addr.postind == 0)
{
- if (operand->type != AARCH64_OPND_ADDR_SIMPLE_2 && operand->addr.writeback)
+ if (operand->addr.writeback)
{
/* Reject [Rn]! */
set_syntax_error (_("missing offset in the pre-indexed address"));
@@ -6148,7 +6146,6 @@ parse_operands (char *str, const aarch64_opcode *opcode)
break;
case AARCH64_OPND_ADDR_SIMPLE:
- case AARCH64_OPND_ADDR_SIMPLE_2:
case AARCH64_OPND_SIMD_ADDR_SIMPLE:
{
/* [<Xn|SP>{, #<simm>}] */
@@ -6158,8 +6155,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
po_misc_or_fail (parse_address (&str, info));
if (info->addr.pcrel || info->addr.offset.is_reg
|| !info->addr.preind || info->addr.postind
- || (info->addr.writeback
- && operands[i] != AARCH64_OPND_ADDR_SIMPLE_2))
+ || info->addr.writeback)
{
set_syntax_error (_("invalid addressing mode"));
goto failure;
@@ -6182,8 +6178,6 @@ parse_operands (char *str, const aarch64_opcode *opcode)
}
}
po_char_or_fail (']');
- if (operands[i] == AARCH64_OPND_ADDR_SIMPLE_2)
- po_char_or_fail ('!');
break;
}
@@ -6782,13 +6776,6 @@ warn_unpredictable_ldst (aarch64_instruction *instr, char *str)
as_warn (_("unpredictable transfer with writeback -- `%s'"), str);
break;
- case ldstgv_indexed:
- /* Load operations must load different registers. */
- if ((opcode->opcode & (1 << 22))
- && opnds[0].reg.regno == opnds[1].addr.base_regno)
- as_warn (_("unpredictable load of register -- `%s'"), str);
- break;
-
case ldstpair_off:
case ldstnapair_offs:
case ldstpair_indexed:
diff --git a/gas/testsuite/gas/aarch64/armv8_5-a-memtag.d b/gas/testsuite/gas/aarch64/armv8_5-a-memtag.d
index fa56bfa64c984da329c150b24852a2278d559b85..363bbe2eb3b1da373737c7d6efce9eba3b6bb6a1 100644
--- a/gas/testsuite/gas/aarch64/armv8_5-a-memtag.d
+++ b/gas/testsuite/gas/aarch64/armv8_5-a-memtag.d
@@ -121,14 +121,3 @@ Disassembly of section \.text:
.*: d960001f ldg xzr, \[x0\]
.*: d96ff000 ldg x0, \[x0, #4080\]
.*: d9700000 ldg x0, \[x0, #-4096\]
-.*: d9e0001b ldgv x27, \[x0\]!
-.*: d9e00360 ldgv x0, \[x27\]!
-.*: d9e00379 ldgv x25, \[x27\]!
-.*: d9e003e0 ldgv x0, \[sp\]!
-.*: d9e0001f ldgv xzr, \[x0\]!
-.*: d9a00000 stgv x0, \[x0\]!
-.*: d9a0001b stgv x27, \[x0\]!
-.*: d9a00360 stgv x0, \[x27\]!
-.*: d9a00379 stgv x25, \[x27\]!
-.*: d9a003e0 stgv x0, \[sp\]!
-.*: d9a0001f stgv xzr, \[x0\]!
diff --git a/gas/testsuite/gas/aarch64/armv8_5-a-memtag.s b/gas/testsuite/gas/aarch64/armv8_5-a-memtag.s
index 2c2ff8f44460ee9b818efb4b7b7510846a46c136..62c9436d78fea63a8ac45126c5f85416a1487822 100644
--- a/gas/testsuite/gas/aarch64/armv8_5-a-memtag.s
+++ b/gas/testsuite/gas/aarch64/armv8_5-a-memtag.s
@@ -30,14 +30,6 @@ func:
\op [sp], #-4096
.endm
- .macro expand_ldg_bulk op
- \op x27, [x0]!
- \op x0, [x27]!
- \op x25, [x27]!
- \op x0, [sp]!
- \op xzr, [x0]!
- .endm
-
# IRG
expand_3_reg irg
irg sp, x0
@@ -106,8 +98,3 @@ func:
ldg xzr, [x0, #0]
ldg x0, [x0, #4080]
ldg x0, [x0, #-4096]
-
- expand_ldg_bulk ldgv
-
- stgv x0, [x0]!
- expand_ldg_bulk stgv
diff --git a/gas/testsuite/gas/aarch64/illegal-memtag.l b/gas/testsuite/gas/aarch64/illegal-memtag.l
index 0d499d9ee955d97183dacab50223a692f2e9d080..dfdf00aba1ea3e21c29ca602de30336b3f00859b 100644
--- a/gas/testsuite/gas/aarch64/illegal-memtag.l
+++ b/gas/testsuite/gas/aarch64/illegal-memtag.l
@@ -12,9 +12,6 @@
[^:]*:[0-9]+: Error: immediate offset out of range -1024 to 1008 at operand 3 -- `stgp x1,x2,\[x3,#1009\]'
[^:]*:[0-9]+: Error: immediate value must be a multiple of 16 at operand 3 -- `stgp x1,x2,\[x3,#33\]'
[^:]*:[0-9]+: Error: immediate offset out of range -1024 to 1008 at operand 3 -- `stgp x1,x2,\[x3,#-1025\]'
-[^:]*:[0-9]+: Warning: unpredictable load of register -- `ldgv x1,\[x1\]!'
-[^:]*:[0-9]+: Error: operand 2 must be a writeback address with base register \(no offset\) -- `ldgv x1,\[x2\]'
-[^:]*:[0-9]+: Error: operand 2 must be a writeback address with base register \(no offset\) -- `stgv x1,\[x2\]'
[^:]*:[0-9]+: Error: operand 1 must be an integer or stack pointer register -- `irg xzr,x2,x3'
[^:]*:[0-9]+: Error: operand 2 must be an integer or stack pointer register -- `irg x1,xzr,x3'
[^:]*:[0-9]+: Error: operand 3 must be an integer register -- `irg x1,x2,sp'
@@ -40,7 +37,3 @@
[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 3 -- `stgp x0,x0,\[xzr\]'
[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `ldg sp,\[x0,#16\]'
[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 2 -- `ldg x0,\[xzr,#16\]'
-[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `ldgv sp,\[x1\]!'
-[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 2 -- `ldgv x0,\[xzr\]!'
-[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `stgv sp,\[x1\]!'
-[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 2 -- `stgv x0,\[xzr\]!'
diff --git a/gas/testsuite/gas/aarch64/illegal-memtag.s b/gas/testsuite/gas/aarch64/illegal-memtag.s
index 7b7dcd94a1a05dbcf5e603b08e6a95835efc5470..35d1b12870bee105ede52d86b392afc68c8190d0 100644
--- a/gas/testsuite/gas/aarch64/illegal-memtag.s
+++ b/gas/testsuite/gas/aarch64/illegal-memtag.s
@@ -20,14 +20,6 @@ func:
stgp x1, x2, [x3, #33]
stgp x1, x2, [x3, #-1025]
- # LDGV : Warn for Xt == Xn
- # STGV : Sould not warn for above
- ldgv x1, [x1]!
- stgv x1, [x1]!
- # Error for no writeback
- ldgv x1, [x2]
- stgv x1, [x2]
-
# Illegal SP/XZR registers
irg xzr, x2, x3
irg x1, xzr, x3
@@ -54,7 +46,3 @@ func:
stgp x0, x0, [xzr]
ldg sp, [x0, #16]
ldg x0, [xzr, #16]
- ldgv sp, [x1]!
- ldgv x0, [xzr]!
- stgv sp, [x1]!
- stgv x0, [xzr]!
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 77e9c10b2fe046389241199c768cf9926f2be8fb..0c0234ab20925dbfe2e008387268bb0b335fe049 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -275,7 +275,6 @@ enum aarch64_opnd
AARCH64_OPND_ADDR_PCREL26, /* 26-bit PC-relative address for e.g. BL. */
AARCH64_OPND_ADDR_SIMPLE, /* Address of ld/st exclusive. */
- AARCH64_OPND_ADDR_SIMPLE_2, /* Address of ld/stgv. */
AARCH64_OPND_ADDR_REGOFF, /* Address of register offset. */
AARCH64_OPND_ADDR_SIMM7, /* Address of signed 7-bit immediate. */
AARCH64_OPND_ADDR_SIMM9, /* Address of signed 9-bit immediate. */
@@ -562,7 +561,6 @@ enum aarch64_insn_class
ldstnapair_offs,
ldstpair_off,
ldstpair_indexed,
- ldstgv_indexed,
loadlit,
log_imm,
log_shift,
diff --git a/opcodes/aarch64-asm.h b/opcodes/aarch64-asm.h
index 0ccbc093dfcedcc49b6a3b94fbb544dc5b76a404..e9520e78fca5b98b48f0eebe05b70fc3a0d7f833 100644
--- a/opcodes/aarch64-asm.h
+++ b/opcodes/aarch64-asm.h
@@ -59,7 +59,6 @@ AARCH64_DECL_OPD_INSERTER (ins_limm);
AARCH64_DECL_OPD_INSERTER (ins_inv_limm);
AARCH64_DECL_OPD_INSERTER (ins_ft);
AARCH64_DECL_OPD_INSERTER (ins_addr_simple);
-AARCH64_DECL_OPD_INSERTER (ins_addr_simple_2);
AARCH64_DECL_OPD_INSERTER (ins_addr_offset);
AARCH64_DECL_OPD_INSERTER (ins_addr_regoff);
AARCH64_DECL_OPD_INSERTER (ins_addr_simm);
diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c
index da1750b94e9db54fe6a4ec0c6261c11b595e37bb..2424b66d9662718fb7a5475972ba57c9595954dd 100644
--- a/opcodes/aarch64-asm.c
+++ b/opcodes/aarch64-asm.c
@@ -618,17 +618,6 @@ aarch64_ins_addr_simple (const aarch64_operand *self ATTRIBUTE_UNUSED,
return TRUE;
}
-/* Encode the address operand for e.g. STGV <Xt>, [<Xn|SP>]!. */
-bfd_boolean
-aarch64_ins_addr_simple_2 (const aarch64_operand *self,
- const aarch64_opnd_info *info, aarch64_insn *code,
- const aarch64_inst *inst,
- aarch64_operand_error *errors)
-
-{
- return aarch64_ins_addr_simple (self, info, code, inst, errors);
-}
-
/* Encode the address operand for e.g.
STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
bfd_boolean
diff --git a/opcodes/aarch64-dis.h b/opcodes/aarch64-dis.h
index 6c7070144209ecd8b08a305f5bf5730009f38883..6df78d9c8c4101fc0154f982e0801e8187705229 100644
--- a/opcodes/aarch64-dis.h
+++ b/opcodes/aarch64-dis.h
@@ -82,7 +82,6 @@ AARCH64_DECL_OPD_EXTRACTOR (ext_limm);
AARCH64_DECL_OPD_EXTRACTOR (ext_inv_limm);
AARCH64_DECL_OPD_EXTRACTOR (ext_ft);
AARCH64_DECL_OPD_EXTRACTOR (ext_addr_simple);
-AARCH64_DECL_OPD_EXTRACTOR (ext_addr_simple_2);
AARCH64_DECL_OPD_EXTRACTOR (ext_addr_offset);
AARCH64_DECL_OPD_EXTRACTOR (ext_addr_regoff);
AARCH64_DECL_OPD_EXTRACTOR (ext_addr_simm);
diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c
index ec19d9202394c4a118b77b522e09b62c51cfb708..4c31f57451d20d8029624e601b15e41cf56f5a19 100644
--- a/opcodes/aarch64-dis.c
+++ b/opcodes/aarch64-dis.c
@@ -985,23 +985,6 @@ aarch64_ext_addr_simple (const aarch64_operand *self ATTRIBUTE_UNUSED,
return TRUE;
}
-
-
-/* Decode the address operand for e.g. STGV <Xt>, [<Xn|SP>]!. */
-bfd_boolean
-aarch64_ext_addr_simple_2 (const aarch64_operand *self ATTRIBUTE_UNUSED,
- aarch64_opnd_info *info,
- aarch64_insn code,
- const aarch64_inst *inst ATTRIBUTE_UNUSED,
- aarch64_operand_error *errors ATTRIBUTE_UNUSED)
-{
- /* Rn */
- info->addr.base_regno = extract_field (FLD_Rn, code, 0);
- info->addr.writeback = 1;
- info->addr.preind = 1;
- return TRUE;
-}
-
/* Decode the address operand for e.g.
stlur <Xt>, [<Xn|SP>{, <amount>}]. */
bfd_boolean
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 38d48225bfdd6bfe8768fdd433a2f1c1c88a9ae0..22839ca72451152db3950b6d9b298a76ece234c4 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -1602,7 +1602,6 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
break;
case ldst_imm9:
case ldstpair_indexed:
- case ldstgv_indexed:
case asisdlsep:
case asisdlsop:
if (opnd->addr.writeback == 0)
@@ -3557,11 +3556,6 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
snprintf (buf, size, "[%s]", name);
break;
- case AARCH64_OPND_ADDR_SIMPLE_2:
- name = get_64bit_int_reg_name (opnd->addr.base_regno, 1);
- snprintf (buf, size, "[%s]!", name);
- break;
-
case AARCH64_OPND_ADDR_REGOFF:
case AARCH64_OPND_SVE_ADDR_R:
case AARCH64_OPND_SVE_ADDR_RR:
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index d1102e23bdae0e0de82a6deb5c20d55806e8fb31..d4ecd6df42033cf05a333e81890c602c1ae7e2a6 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -3324,8 +3324,6 @@ struct aarch64_opcode aarch64_opcode_table[] =
RCPC_INSN ("ldaprb", 0x38bfc000, 0xfffffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0),
RCPC_INSN ("ldaprh", 0x78bfc000, 0xfffffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0),
RCPC_INSN ("ldapr", 0xb8bfc000, 0xbffffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q),
- MEMTAG_INSN ("ldgv", 0xd9e00000, 0xfffffc00, ldstgv_indexed, OP2 (Rt, ADDR_SIMPLE_2), QL_STLX, 0),
- MEMTAG_INSN ("stgv", 0xd9a00000, 0xfffffc00, ldstgv_indexed, OP2 (Rt, ADDR_SIMPLE_2), QL_STLX, 0),
/* Limited Ordering Regions load/store instructions. */
_LOR_INSN ("ldlar", 0x88df7c00, 0xbfe08000, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q),
_LOR_INSN ("ldlarb", 0x08df7c00, 0xffe08000, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0),
@@ -4650,8 +4648,6 @@ struct aarch64_opcode aarch64_opcode_table[] =
F(FLD_imm26), "26-bit PC-relative address") \
Y(ADDRESS, addr_simple, "ADDR_SIMPLE", 0, F(), \
"an address with base register (no offset)") \
- Y(ADDRESS, addr_simple_2, "ADDR_SIMPLE_2", 0, F(), \
- "a writeback address with base register (no offset)") \
Y(ADDRESS, addr_regoff, "ADDR_REGOFF", 0, F(), \
"an address with register offset") \
Y(ADDRESS, addr_simm, "ADDR_SIMM7", 0, F(FLD_imm7,FLD_index2), \