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Re: [PATCH] RISC-V: Add missing c.unimp instruction.
- From: Palmer Dabbelt <palmer at sifive dot com>
- To: Jim Wilson <jimw at sifive dot com>, Andrew Waterman <andrew at sifive dot com>
- Cc: binutils at sourceware dot org, Jim Wilson <jimw at sifive dot com>
- Date: Thu, 29 Nov 2018 17:46:38 -0800 (PST)
- Subject: Re: [PATCH] RISC-V: Add missing c.unimp instruction.
On Thu, 29 Nov 2018 13:11:45 PST (-0800), Jim Wilson wrote:
We have support for unimp to produce 2 or 4 byte instructions depending on
whether compressed support is on, but we don't have a c.unimp to force use
of the 2 byte instruction form, unlike for all of the other compressed
instructions. This patch adds the missing instruction.
This was tested cross for riscv{32,64}-{elf,linux} with builds and make check
runs. There were no regressions.
Committed.
Jim
opcodes/
* riscv-opc.c (unimp): Mark compressed unimp as INSN_ALIAS.
(c.unimp): New.
---
opcodes/riscv-opc.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index a272e29fee..3da2a7702b 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -198,7 +198,7 @@ match_srxi_as_c_srxi (const struct riscv_opcode *op, insn_t insn)
const struct riscv_opcode riscv_opcodes[] =
{
/* name, xlen, isa, operands, match, mask, match_func, pinfo. */
-{"unimp", 0, {"C", 0}, "", 0, 0xffffU, match_opcode, 0 },
+{"unimp", 0, {"C", 0}, "", 0, 0xffffU, match_opcode, INSN_ALIAS },
{"unimp", 0, {"I", 0}, "", MATCH_CSRRW | (CSR_CYCLE << OP_SH_CSR), 0xffffffffU, match_opcode, 0 }, /* csrw cycle, x0 */
I think this is an alias: the ISA manual doesn't actually define a single
canonical unimplemented instruction, this is just an instruction that is not
listed in the ISA spec and is unlikely to ever be implemented.
{"ebreak", 0, {"C", 0}, "", MATCH_C_EBREAK, MASK_C_EBREAK, match_opcode, INSN_ALIAS },
{"ebreak", 0, {"I", 0}, "", MATCH_EBREAK, MASK_EBREAK, match_opcode, 0 },
@@ -696,6 +696,7 @@ const struct riscv_opcode riscv_opcodes[] =
{"fcvt.q.lu", 64, {"Q", 0}, "D,s,m", MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU, match_opcode, 0 },
/* Compressed instructions. */
+{"c.unimp", 0, {"C", 0}, "", 0, 0xffffU, match_opcode, 0 },
I think this is also an alias, largely for the same reason.
{"c.ebreak", 0, {"C", 0}, "", MATCH_C_EBREAK, MASK_C_EBREAK, match_opcode, 0 },
{"c.jr", 0, {"C", 0}, "d", MATCH_C_JR, MASK_C_JR, match_rd_nonzero, INSN_BRANCH },
{"c.jalr", 0, {"C", 0}, "d", MATCH_C_JALR, MASK_C_JALR, match_rd_nonzero, INSN_JSR },
This one is explicitly listed in the ISA manual as an illegal instruction, so
it's correct to not be an alias.