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Re: [PATCH, BINUTILS, AARCH64, 8/8] Add data cache instructions for Memory Tagging Extension


Hi Richard and Christophe

Thank you for the review comments on the whole patch series. I will
re-work some of the test cases as asked and re-post the patch shortly.
I will update the MEMTAG, blank space and typo issues locally before
applying them.

Thanks
Sudi

On 30/10/18 10:28, Richard Earnshaw (lists) wrote:
> On 09/10/2018 18:26, Sudakshina Das wrote:
>> Hi
>>
>> This patch is part of the patch series to add support for ARMv8.5-A
>> Memory Tagging Extensions.
>> (https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools)
>>
>> Memory Tagging Extension (MTE) is an optional extension to
>> ARMv8.5-A and is enabled using the +memtag command line option.
>>
>> This patch adds all the data cache instructions that are part of this
>> extension:
>> - DC IGVAC, Xt
>> - DC IGSW, Xt
>> - DC CGSW, Xt
>> - DC CIGSW, Xt
>> - DC CGVAC, Xt
>> - DC CGVAP, Xt
>> - DC CGVADP, Xt
>> - DC CIGVAC, Xt
>> - DC GVA, Xt
>> - DC IGDVAC, Xt
>> - DC IGDSW, Xt
>> - DC CGDSW, Xt
>> - DC CIGDSW, Xt
>> - DC CGDVAC, Xt
>> - DC CGDVAP, Xt
>> - DC CGDVADP, Xt
>> - DC CIGDVAC, Xt
>> - DC GZVA, Xt
>>
>> Testing done: Builds and reg tests all pass on aarch64-none-linux-gnu.
>> Added test.
>>
>> Is this ok for trunk?
>>
>> Thanks
>> Sudi
>>
>> *** opcodes/ChangeLog ***
>>
>> 2018-xx-xx  Sudakshina Das  <sudi.das@arm.com>
>>
>>      * aarch64-opc.c (aarch64_sys_regs_dc): New entries for
>>      IGVAC, IGSW, CGSW, CIGSW, CGVAC, CGVAP, CGVADP, CIGVAC, GVA,
>>      IGDVAC, IGDSW, CGDSW, CIGDSW, CGDVAC, CGDVAP, CGDVADP,
>>      CIGDVAC and GZVA.
>>      (aarch64_sys_ins_reg_supported_p): New check for above.
>>
>> *** gas/ChangeLog ***
>>
>> 2018-xx-xx  Sudakshina Das  <sudi.das@arm.com>
>>
>>      * testsuite/gas/aarch64/sysreg-4.s: Test IGVAC, IGSW,
>>      CGSW, CIGSW, CGVAC, CGVAP, CGVADP, CIGVAC, GVA,
>>      IGDVAC, IGDSW, CGDSW, CIGDSW, CGDVAC, CGDVAP, CGDVADP,
>>      CIGDVAC and GZVA with DC.
>>      * testsuite/gas/aarch64/sysreg-4.d: Likewise.
>>      * testsuite/gas/aarch64/illegal-sysreg-4.l: Likewise.
>>
>>
>>
>> rb10040.patch
>>
>> diff --git a/gas/testsuite/gas/aarch64/illegal-sysreg-4.l b/gas/testsuite/gas/aarch64/illegal-sysreg-4.l
>> index 36abf4f5b18b14881297230df3bdcea240a4b0b9..d431f9bfc57a1292cb2221f708e63d4e9d2ec401 100644
>> --- a/gas/testsuite/gas/aarch64/illegal-sysreg-4.l
>> +++ b/gas/testsuite/gas/aarch64/illegal-sysreg-4.l
>> @@ -35,3 +35,21 @@
>>   [^:]*:[0-9]+: Error: selected processor does not support system register name 'rgsr_el1'
>>   [^:]*:[0-9]+: Error: selected processor does not support system register name 'gcr_el1'
>>   [^:]*:[0-9]+: Error: selected processor does not support PSTATE field name 'tco'
>> +[^:]*:[0-9]+: Error: selected processor does not support system register name 'igvac'
>> +[^:]*:[0-9]+: Error: selected processor does not support system register name 'igsw'
>> +[^:]*:[0-9]+: Error: selected processor does not support system register name 'cgsw'
>> +[^:]*:[0-9]+: Error: selected processor does not support system register name 'cigsw'
>> +[^:]*:[0-9]+: Error: selected processor does not support system register name 'cgvac'
>> +[^:]*:[0-9]+: Error: selected processor does not support system register name 'cgvap'
>> +[^:]*:[0-9]+: Error: selected processor does not support system register name 'cgvadp'
>> +[^:]*:[0-9]+: Error: selected processor does not support system register name 'cigvac'
>> +[^:]*:[0-9]+: Error: selected processor does not support system register name 'gva'
>> +[^:]*:[0-9]+: Error: selected processor does not support system register name 'igdvac'
>> +[^:]*:[0-9]+: Error: selected processor does not support system register name 'igdsw'
>> +[^:]*:[0-9]+: Error: selected processor does not support system register name 'cgdsw'
>> +[^:]*:[0-9]+: Error: selected processor does not support system register name 'cigdsw'
>> +[^:]*:[0-9]+: Error: selected processor does not support system register name 'cgdvac'
>> +[^:]*:[0-9]+: Error: selected processor does not support system register name 'cgdvap'
>> +[^:]*:[0-9]+: Error: selected processor does not support system register name 'cgdvadp'
>> +[^:]*:[0-9]+: Error: selected processor does not support system register name 'cigdvac'
>> +[^:]*:[0-9]+: Error: selected processor does not support system register name 'gzva'
>> diff --git a/gas/testsuite/gas/aarch64/sysreg-4.d b/gas/testsuite/gas/aarch64/sysreg-4.d
>> index 0abeed8322ff9876cb53712df4f866d27537840d..ab6e217fc1beb0d59744eab987e537430f128d57 100644
>> --- a/gas/testsuite/gas/aarch64/sysreg-4.d
>> +++ b/gas/testsuite/gas/aarch64/sysreg-4.d
>> @@ -38,3 +38,21 @@ Disassembly of section \.text:
>>   .*:	d51810a1 	msr	rgsr_el1, x1
>>   .*:	d51810c3 	msr	gcr_el1, x3
>>   .*:	d503489f 	msr	tco, #0x8
>> +.*:	d5087661 	dc	igvac, x1
>> +.*:	d5087682 	dc	igsw, x2
>> +.*:	d5087a83 	dc	cgsw, x3
>> +.*:	d5087e84 	dc	cigsw, x4
>> +.*:	d50b7a65 	dc	cgvac, x5
>> +.*:	d50b7c66 	dc	cgvap, x6
>> +.*:	d50b7d67 	dc	cgvadp, x7
>> +.*:	d50b7e68 	dc	cigvac, x8
>> +.*:	d50b7469 	dc	gva, x9
>> +.*:	d50876aa 	dc	igdvac, x10
>> +.*:	d50876cb 	dc	igdsw, x11
>> +.*:	d5087acc 	dc	cgdsw, x12
>> +.*:	d5087ecd 	dc	cigdsw, x13
>> +.*:	d50b7aae 	dc	cgdvac, x14
>> +.*:	d50b7caf 	dc	cgdvap, x15
>> +.*:	d50b7db0 	dc	cgdvadp, x16
>> +.*:	d50b7eb1 	dc	cigdvac, x17
>> +.*:	d50b7492 	dc	gzva, x18
>> diff --git a/gas/testsuite/gas/aarch64/sysreg-4.s b/gas/testsuite/gas/aarch64/sysreg-4.s
>> index d25e9b91dfe5faf7891453096a48e61de0ab96b9..6c18b4a4e402827b960b058b45cb538c8e48cbe8 100644
>> --- a/gas/testsuite/gas/aarch64/sysreg-4.s
>> +++ b/gas/testsuite/gas/aarch64/sysreg-4.s
>> @@ -38,3 +38,26 @@ func:
>>   
>>   	# MSR (immediate)
>>   	msr TCO, #8
>> +
>> +	# Data cache
>> +	dc igvac, x1
>> +	dc igsw, x2
>> +	dc cgsw, x3
>> +	dc cigsw, x4
>> +	dc cgvac, x5
>> +	dc cgvap, x6
>> +	dc cgvadp, x7
>> +	dc cigvac, x8
>> +
>> +	dc gva, x9
>> +
>> +	dc igdvac, x10
>> +	dc igdsw, x11
>> +	dc cgdsw, x12
>> +	dc cigdsw, x13
>> +	dc cgdvac, x14
>> +	dc cgdvap, x15
>> +	dc cgdvadp, x16
>> +	dc cigdvac, x17
>> +
>> +	dc gzva, x18
>> diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
>> index edd5b2d09d05bf2e92a247b87becb1d16fe4c0be..40a7d20b7467783ae28fac71e79478196578f43b 100644
>> --- a/opcodes/aarch64-opc.c
>> +++ b/opcodes/aarch64-opc.c
>> @@ -4458,15 +4458,33 @@ const aarch64_sys_ins_reg aarch64_sys_regs_ic[] =
>>   const aarch64_sys_ins_reg aarch64_sys_regs_dc[] =
>>   {
>>       { "zva",	    CPENS (3, C7, C4, 1),  F_HASXT },
>> +    { "gva",	    CPENS (3, C7, C4, 3),  F_HASXT | F_ARCHEXT },
>> +    { "gzva",	    CPENS (3, C7, C4, 4),  F_HASXT | F_ARCHEXT },
>>       { "ivac",       CPENS (0, C7, C6, 1),  F_HASXT },
>> +    { "igvac",      CPENS (0, C7, C6, 3),  F_HASXT | F_ARCHEXT },
>> +    { "igsw",       CPENS (0, C7, C6, 4),  F_HASXT | F_ARCHEXT },
>>       { "isw",	    CPENS (0, C7, C6, 2),  F_HASXT },
>> +    { "igdvac",	    CPENS (0, C7, C6, 5),  F_HASXT | F_ARCHEXT },
>> +    { "igdsw",	    CPENS (0, C7, C6, 6),  F_HASXT | F_ARCHEXT },
>>       { "cvac",       CPENS (3, C7, C10, 1), F_HASXT },
>> +    { "cgvac",      CPENS (3, C7, C10, 3), F_HASXT | F_ARCHEXT },
>> +    { "cgdvac",     CPENS (3, C7, C10, 5), F_HASXT | F_ARCHEXT },
>>       { "csw",	    CPENS (0, C7, C10, 2), F_HASXT },
>> +    { "cgsw",       CPENS (0, C7, C10, 4), F_HASXT | F_ARCHEXT },
>> +    { "cgdsw",	    CPENS (0, C7, C10, 6), F_HASXT | F_ARCHEXT },
>>       { "cvau",       CPENS (3, C7, C11, 1), F_HASXT },
>>       { "cvap",       CPENS (3, C7, C12, 1), F_HASXT | F_ARCHEXT },
>> +    { "cgvap",      CPENS (3, C7, C12, 3), F_HASXT | F_ARCHEXT },
>> +    { "cgdvap",     CPENS (3, C7, C12, 5), F_HASXT | F_ARCHEXT },
>>       { "cvadp",      CPENS (3, C7, C13, 1), F_HASXT | F_ARCHEXT },
>> +    { "cgvadp",     CPENS (3, C7, C13, 3), F_HASXT | F_ARCHEXT },
>> +    { "cgdvadp",    CPENS (3, C7, C13, 5), F_HASXT | F_ARCHEXT },
>>       { "civac",      CPENS (3, C7, C14, 1), F_HASXT },
>> +    { "cigvac",     CPENS (3, C7, C14, 3), F_HASXT | F_ARCHEXT },
>> +    { "cigdvac",    CPENS (3, C7, C14, 5), F_HASXT | F_ARCHEXT },
>>       { "cisw",       CPENS (0, C7, C14, 2), F_HASXT },
>> +    { "cigsw",      CPENS (0, C7, C14, 4), F_HASXT | F_ARCHEXT },
>> +    { "cigdsw",     CPENS (0, C7, C14, 6), F_HASXT | F_ARCHEXT },
>>       { 0,       CPENS(0,0,0,0), 0 }
>>   };
>>   
>> @@ -4605,6 +4623,28 @@ aarch64_sys_ins_reg_supported_p (const aarch64_feature_set features,
>>         && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_CVADP))
>>       return FALSE;
>>   
>> +  /* DC <dc_op> for ARMv8.5-A Memory Tagging Extension.  */
>> +  if ((reg->value == CPENS (0, C7, C6, 3)
>> +       || reg->value == CPENS (0, C7, C6, 4)
>> +       || reg->value == CPENS (0, C7, C10, 4)
>> +       || reg->value == CPENS (0, C7, C14, 4)
>> +       || reg->value == CPENS (3, C7, C10, 3)
>> +       || reg->value == CPENS (3, C7, C12, 3)
>> +       || reg->value == CPENS (3, C7, C13, 3)
>> +       || reg->value == CPENS (3, C7, C14, 3)
>> +       || reg->value == CPENS (3, C7, C4, 3)
>> +       || reg->value == CPENS (0, C7, C6, 5)
>> +       || reg->value == CPENS (0, C7, C6, 6)
>> +       || reg->value == CPENS (0, C7, C10, 6)
>> +       || reg->value == CPENS (0, C7, C14, 6)
>> +       || reg->value == CPENS (3, C7, C10, 5)
>> +       || reg->value == CPENS (3, C7, C12, 5)
>> +       || reg->value == CPENS (3, C7, C13, 5)
>> +       || reg->value == CPENS (3, C7, C14, 5)
>> +       || reg->value == CPENS (3, C7, C4, 4))
>> +      && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_MTE))
>> +    return FALSE;
>> +
>>     /* AT S1E1RP, AT S1E1WP.  Values are from aarch64_sys_regs_at.  */
>>     if ((reg->value == CPENS (0, C7, C9, 0)
>>          || reg->value == CPENS (0, C7, C9, 1))
>>
>>
> 
> 
> OK (modulo MTE).
> 
> R.
> 


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