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[PATCH][AArch64][binutils] Fix SBO bit in disassembly mask for ldrah.
- From: Tamar Christina <tamar dot christina at arm dot com>
- To: binutils at sourceware dot org
- Cc: nd at arm dot com, Richard dot Earnshaw at arm dot com, marcus dot shawcroft at arm dot com
- Date: Fri, 29 Jun 2018 14:29:07 +0100
- Subject: [PATCH][AArch64][binutils] Fix SBO bit in disassembly mask for ldrah.
Hi All,
The disassembly mask for ldarh incorrectly didn't mask out bit 20 which
is part of the SBO part of the instruction and shouldn't be considered input.
This fixes the wrong bit fixing the disassembly of instructions to
ldarh and makes the behavior consistent.
Build on native hardware and regtested on
aarch64-none-elf, aarch64-none-elf (32 bit host),
aarch64-none-linux-gnu, aarch64_be-none-linux-gnu
Cross-compiled and regtested on
aarch64-none-linux-gnu, aarch64_be-none-linux-gnu
and no issues.
Ok for master? and for backport to binutils-2.31?
Thanks,
Tamar
opcodes/
2018-06-29 Tamar Christina <tamar.christina@arm.com>
PR binutils/23242
* aarch64-tbl.h (ldarh): Fix disassembly mask.
--
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 08eec60783b5fdf5663f28fa1c777f8578ec9e06..672e1ee5f4a3a75a2d92f047a98d7336b11357d0 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -3219,7 +3219,7 @@ struct aarch64_opcode aarch64_opcode_table[] =
CORE_INSN ("ldxrh", 0x485f7c00, 0xffe08000, ldstexcl, 0, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0),
CORE_INSN ("ldaxrh", 0x485ffc00, 0xffe08000, ldstexcl, 0, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0),
CORE_INSN ("stlrh", 0x489ffc00, 0xffe08000, ldstexcl, 0, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0),
- CORE_INSN ("ldarh", 0x48dffc00, 0xffeffc00, ldstexcl, 0, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0),
+ CORE_INSN ("ldarh", 0x48dffc00, 0xfffffc00, ldstexcl, 0, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0),
CORE_INSN ("stxr", 0x88007c00, 0xbfe08000, ldstexcl, 0, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2_LDST_EXC, F_GPRSIZE_IN_Q),
CORE_INSN ("stlxr", 0x8800fc00, 0xbfe08000, ldstexcl, 0, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2_LDST_EXC, F_GPRSIZE_IN_Q),
CORE_INSN ("stxp", 0x88200000, 0xbfe08000, ldstexcl, 0, OP4 (Rs, Rt, Rt2, ADDR_SIMPLE), QL_R3_LDST_EXC, F_GPRSIZE_IN_Q),