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[PATCH v3] MIPS: Add Global INValidate ASE support
- From: Faraz Shahbazker <Faraz dot Shahbazker at mips dot com>
- To: Maciej Rozycki <Maciej dot Rozycki at mips dot com>, "binutils at sourceware dot org" <binutils at sourceware dot org>
- Cc: Matthew Fortune <Matthew dot Fortune at mips dot com>
- Date: Wed, 13 Jun 2018 19:30:08 +0000
- Subject: [PATCH v3] MIPS: Add Global INValidate ASE support
- References: <1d3f8dba-f97e-5471-a2c0-8d9282e87724@mips.com> <4219DBDA9D67EF429BA5C9BBA5A8E9C6031AB1C5@MIPSMAIL01.mipstec.com> <alpine.DEB.2.00.1711302114500.31156@tp.orcam.me.uk>
Add support for the Global INValidate Application Specific Extension
for Release 6 of the MIPS Architecture.
[1] "MIPS Architecture for Programmers Volume II-A: The MIPS32
Instruction Set Manual", Imagination Technologies Ltd., Document
Number: MD00086, Revision 6.06, December 15, 2016, Section 3.2
"Alphabetical List of Instructions", pp. 187-191
bfd/
* elfxx-mips.c (print_mips_ases): Add GINV extension.
binutils/
* readelf.c (print_mips_ases) Add GINV extension.
gas/
* config/tc-mips.c (options): Add OPTION_GINV and OPTION_NO_GINV.
(md_longopts): Likewise.
(mips_ases): Define availability for GINV.
(mips_convert_ase_flags): Map ASE_GINV to AFL_ASE_GINV.
(md_show_usage): Add help for -mginv and -mno-ginv.
* doc/as.texinfo: Document -mginv, -mno-ginv.
* doc/c-mips.texi: Document -mginv, -mno-ginv, .set ginv and
.set noginv.
* testsuite/gas/mips/ase-errors-1.s: Add error checks for GINV
ASE.
* testsuite/gas/mips/ase-errors-2.s: Likewise.
* testsuite/gas/mips/ase-errors-1.l: Likewise.
* testsuite/gas/mips/ase-errors-2.l: Likewise.
* testsuite/gas/mips/ginv.d: New test.
* testsuite/gas/mips/ginv-err.d: New test.
* testsuite/gas/mips/ginv-err.l: New test stderr output.
* testsuite/gas/mips/ginv.s: New test source.
* testsuite/gas/mips/ginv-err.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
include/
* elf/mips.h (AFL_ASE_GINV, AFL_ASE_RESERVED1): New macros.
(AFL_ASE_MASK): Update to include AFL_ASE_GINV.
* opcode/mips.h: Comments describing new MIPS operand format "+\".
(ASE_GINV): New macro.
opcodes/
* mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
mips64r6 descriptors.
(parse_mips_ase_option): Handle -Mginv option.
(print_mips_disassembler_options): Document -Mginv.
* mips-opc.c (decode_mips_operand) <+\>: New operand format.
(GINV): New macro.
(mips_opcodes): Define ginvi and ginvt.
---
Updated patch v3, for review
The new ginv* instructions are described in Section 3.2 of the MIPS
Instruction Set v6.06:
https://www.mips.com/?do-download=the-mips32-instruction-set-v6-06
Summary of changes:
* New instruction GINVI, GINVT: enabled by option `-mginv'.
* Bit-17 in MIPS.abiflags is set when GINV extension is enabled.
Significant changes w.r.t. patch v2:
* Remove unpublished variations of ginv* instructions (VZ, microMIPS).
* Print GINV in MIPS ASE flags.
Note that bit 16 (mask 0x10000) in the ases word of the MIPS ABI flags
structure is reserved by MIPS Tech for an ASE which is waiting to be
published. Rather than keep an unspecified gap in the ases word, this
bit has been marked with the place-holder AFL_ASE_RESERVED1 for now.
---
bfd/elfxx-mips.c | 2 ++
binutils/readelf.c | 2 ++
gas/NEWS | 2 ++
gas/config/tc-mips.c | 14 ++++++++++++++
gas/doc/as.texinfo | 7 +++++++
gas/doc/c-mips.texi | 13 +++++++++++++
gas/testsuite/gas/mips/ase-errors-1.l | 4 ++++
gas/testsuite/gas/mips/ase-errors-1.s | 8 ++++++++
gas/testsuite/gas/mips/ase-errors-2.l | 4 ++++
gas/testsuite/gas/mips/ase-errors-2.s | 8 ++++++++
gas/testsuite/gas/mips/ginv-err.d | 3 +++
gas/testsuite/gas/mips/ginv-err.l | 4 ++++
gas/testsuite/gas/mips/ginv-err.s | 5 +++++
gas/testsuite/gas/mips/ginv.d | 18 ++++++++++++++++++
gas/testsuite/gas/mips/ginv.s | 9 +++++++++
gas/testsuite/gas/mips/mips.exp | 3 +++
include/elf/mips.h | 4 +++-
include/opcode/mips.h | 7 ++++++-
opcodes/mips-dis.c | 14 ++++++++++++--
opcodes/mips-opc.c | 8 ++++++++
20 files changed, 135 insertions(+), 4 deletions(-)
create mode 100644 gas/testsuite/gas/mips/ginv-err.d
create mode 100644 gas/testsuite/gas/mips/ginv-err.l
create mode 100644 gas/testsuite/gas/mips/ginv-err.s
create mode 100644 gas/testsuite/gas/mips/ginv.d
create mode 100644 gas/testsuite/gas/mips/ginv.s
diff --git a/bfd/elfxx-mips.c b/bfd/elfxx-mips.c
index 205faa6..5554698 100644
--- a/bfd/elfxx-mips.c
+++ b/bfd/elfxx-mips.c
@@ -15643,6 +15643,8 @@ print_mips_ases (FILE *file, unsigned int mask)
fputs ("\n\tMIPS16e2 ASE", file);
if (mask & AFL_ASE_CRC)
fputs ("\n\tCRC ASE", file);
+ if (mask & AFL_ASE_GINV)
+ fputs ("\n\tGINV ASE", file);
if (mask == 0)
fprintf (file, "\n\t%s", _("None"));
else if ((mask & ~AFL_ASE_MASK) != 0)
diff --git a/binutils/readelf.c b/binutils/readelf.c
index 3af729f..9971307 100644
--- a/binutils/readelf.c
+++ b/binutils/readelf.c
@@ -15506,6 +15506,8 @@ print_mips_ases (unsigned int mask)
fputs ("\n\tMIPS16e2 ASE", stdout);
if (mask & AFL_ASE_CRC)
fputs ("\n\tCRC ASE", stdout);
+ if (mask & AFL_ASE_GINV)
+ fputs ("\n\tGINV ASE", stdout);
if (mask == 0)
fprintf (stdout, "\n\t%s", _("None"));
else if ((mask & ~AFL_ASE_MASK) != 0)
diff --git a/gas/NEWS b/gas/NEWS
index a50e264..9dfc845 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -1,5 +1,7 @@
-*- text -*-
+* Add support for the MIPS Global INValidate (GINV) ASE.
+
* Add support for the MIPS Cyclic Redudancy Check (CRC) ASE.
* Add support for the Freescale S12Z architecture.
diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
index 7cadbb6..8dfc1f5 100644
--- a/gas/config/tc-mips.c
+++ b/gas/config/tc-mips.c
@@ -1527,6 +1527,8 @@ enum options
OPTION_NAN,
OPTION_ODD_SPREG,
OPTION_NO_ODD_SPREG,
+ OPTION_GINV,
+ OPTION_NO_GINV,
OPTION_END_OF_ENUM
};
@@ -1585,6 +1587,8 @@ struct option md_longopts[] =
{"mno-mips16e2", no_argument, NULL, OPTION_NO_MIPS16E2},
{"mcrc", no_argument, NULL, OPTION_CRC},
{"mno-crc", no_argument, NULL, OPTION_NO_CRC},
+ {"mginv", no_argument, NULL, OPTION_GINV},
+ {"mno-ginv", no_argument, NULL, OPTION_NO_GINV},
/* Old-style architecture options. Don't add more of these. */
{"m4650", no_argument, NULL, OPTION_M4650},
@@ -1777,6 +1781,11 @@ static const struct mips_ase mips_ases[] = {
OPTION_CRC, OPTION_NO_CRC,
6, 6, -1, -1,
-1 },
+
+ { "ginv", ASE_GINV, 0,
+ OPTION_GINV, OPTION_NO_GINV,
+ 6, 6, 6, 6,
+ -1 },
};
/* The set of ASEs that require -mfp64. */
@@ -18987,6 +18996,8 @@ mips_convert_ase_flags (int ase)
ext_ases |= file_ase_mips16 ? AFL_ASE_MIPS16E2 : 0;
if (ase & ASE_CRC)
ext_ases |= AFL_ASE_CRC;
+ if (ase & ASE_GINV)
+ ext_ases |= AFL_ASE_GINV;
return ext_ases;
}
@@ -20004,6 +20015,9 @@ MIPS options:\n\
-mcrc generate CRC instructions\n\
-mno-crc do not generate CRC instructions\n"));
fprintf (stream, _("\
+-mginv generate Global INValidate (GINV) instructions\n\
+-mno-ginv do not generate Global INValidate instructions\n"));
+ fprintf (stream, _("\
-minsn32 only generate 32-bit microMIPS instructions\n\
-mno-insn32 generate all microMIPS instructions\n"));
fprintf (stream, _("\
diff --git a/gas/doc/as.texinfo b/gas/doc/as.texinfo
index 1c40a1e..493049c 100644
--- a/gas/doc/as.texinfo
+++ b/gas/doc/as.texinfo
@@ -423,6 +423,7 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}.
[@b{-mmt}] [@b{-mno-mt}]
[@b{-mmcu}] [@b{-mno-mcu}]
[@b{-mcrc}] [@b{-mno-crc}]
+ [@b{-mginv}] [@b{-mno-ginv}]
[@b{-minsn32}] [@b{-mno-insn32}]
[@b{-mfix7000}] [@b{-mno-fix7000}]
[@b{-mfix-rm7000}] [@b{-mno-fix-rm7000}]
@@ -1519,6 +1520,12 @@ Generate code for the MIPS cyclic redundancy check (CRC) Application
Specific Extension. This tells the assembler to accept CRC instructions.
@samp{-mno-crc} turns off this option.
+@item -mginv
+@itemx -mno-ginv
+Generate code for the Global INValidate (GINV) Application Specific
+Extension. This tells the assembler to accept GINV instructions.
+@samp{-mno-ginv} turns off this option.
+
@item -minsn32
@itemx -mno-insn32
Only use 32-bit instruction encodings when generating code for the
diff --git a/gas/doc/c-mips.texi b/gas/doc/c-mips.texi
index 36997e9..9cbfaf2 100644
--- a/gas/doc/c-mips.texi
+++ b/gas/doc/c-mips.texi
@@ -240,6 +240,12 @@ Generate code for the cyclic redundancy check (CRC) Application Specific
Extension. This tells the assembler to accept CRC instructions.
@samp{-mno-crc} turns off this option.
+@item -mginv
+@itemx -mno-ginv
+Generate code for the Global INValidate (GINV) Application Specific
+Extension. This tells the assembler to accept GINV instructions.
+@samp{-mno-ginv} turns off this option.
+
@item -minsn32
@itemx -mno-insn32
Only use 32-bit instruction encodings when generating code for the
@@ -1124,6 +1130,13 @@ The directive @code{.set crc} makes the assembler accept instructions
from the CRC Extension from that point on in the assembly. The
@code{.set nocrc} directive prevents CRC instructions from being accepted.
+@cindex MIPS Global INValidate (GINV) instruction generation override
+@kindex @code{.set ginv}
+@kindex @code{.set noginv}
+The directive @code{.set ginv} makes the assembler accept instructions
+from the GINV Extension from that point on in the assembly. The
+@code{.set noginv} directive prevents GINV instructions from being accepted.
+
Traditional MIPS assemblers do not support these directives.
@node MIPS Floating-Point
diff --git a/gas/testsuite/gas/mips/ase-errors-1.l b/gas/testsuite/gas/mips/ase-errors-1.l
index 7f7bba5..2c9fb9e 100644
--- a/gas/testsuite/gas/mips/ase-errors-1.l
+++ b/gas/testsuite/gas/mips/ase-errors-1.l
@@ -44,3 +44,7 @@
.*:108: Error: opcode not supported.* `crc32d \$4,\$7,\$4'
.*:109: Warning: the `crc' extension requires MIPS32 revision 6 or greater
.*:112: Error: opcode not supported.* `crc32b \$4,\$7,\$4'
+# ----------------------------------------------------------------------------
+.*:117: Warning: the `ginv' extension requires MIPS32 revision 6 or greater
+.*:120: Error: opcode not supported.* `ginvi \$a0'
+# ----------------------------------------------------------------------------
diff --git a/gas/testsuite/gas/mips/ase-errors-1.s b/gas/testsuite/gas/mips/ase-errors-1.s
index 811f719..8b679a3 100644
--- a/gas/testsuite/gas/mips/ase-errors-1.s
+++ b/gas/testsuite/gas/mips/ase-errors-1.s
@@ -111,6 +111,14 @@
.set nocrc
crc32b $4,$7,$4 # ERROR: crc not enabled
+ .set mips32r6
+ .set ginv # OK
+ ginvi $a0 # OK
+ .set mips32r5 # ERROR: too low
+ ginvt $a0, 1 # OK
+ .set noginv
+ ginvi $a0 # ERROR: ginv not enabled
+
# There should be no errors after this.
.set fp=32
.set mips1
diff --git a/gas/testsuite/gas/mips/ase-errors-2.l b/gas/testsuite/gas/mips/ase-errors-2.l
index 652c27c..6ac5163 100644
--- a/gas/testsuite/gas/mips/ase-errors-2.l
+++ b/gas/testsuite/gas/mips/ase-errors-2.l
@@ -36,3 +36,7 @@
.*:93: Warning: the `crc' extension requires MIPS64 revision 6 or greater
.*:97: Error: opcode not supported.* `crc32b \$4,\$7,\$4'
.*:98: Error: opcode not supported.* `crc32d \$4,\$7,\$4'
+# ----------------------------------------------------------------------------
+.*:103: Warning: the `ginv' extension requires MIPS64 revision 6 or greater
+.*:106: Error: opcode not supported.* `ginvi \$a0'
+# ----------------------------------------------------------------------------
diff --git a/gas/testsuite/gas/mips/ase-errors-2.s b/gas/testsuite/gas/mips/ase-errors-2.s
index 7ef363e..2b31517 100644
--- a/gas/testsuite/gas/mips/ase-errors-2.s
+++ b/gas/testsuite/gas/mips/ase-errors-2.s
@@ -97,6 +97,14 @@
crc32b $4,$7,$4 # ERROR: crc not enabled
crc32d $4,$7,$4 # ERROR: crc not enabled
+ .set mips64r6
+ .set ginv # OK
+ ginvi $a0 # OK
+ .set mips64r5 # ERROR: too low
+ ginvt $a0,1 # OK
+ .set noginv
+ ginvi $a0 # ERROR: ginv not enabled
+
# There should be no errors after this.
.set fp=32
.set mips4
diff --git a/gas/testsuite/gas/mips/ginv-err.d b/gas/testsuite/gas/mips/ginv-err.d
new file mode 100644
index 0000000..68c4096
--- /dev/null
+++ b/gas/testsuite/gas/mips/ginv-err.d
@@ -0,0 +1,3 @@
+#name: MIPS GINV instruction errors
+#as: -32 -mginv
+#error-output: ginv-err.l
diff --git a/gas/testsuite/gas/mips/ginv-err.l b/gas/testsuite/gas/mips/ginv-err.l
new file mode 100644
index 0000000..dbbb70c
--- /dev/null
+++ b/gas/testsuite/gas/mips/ginv-err.l
@@ -0,0 +1,4 @@
+.*: Assembler messages:
+.*:3: Error: invalid operands `ginvi 2'
+.*:4: Error: invalid operands `ginvt 3,3'
+.*:5: Error: operand 2 out of range `ginvt \$4,4'
diff --git a/gas/testsuite/gas/mips/ginv-err.s b/gas/testsuite/gas/mips/ginv-err.s
new file mode 100644
index 0000000..769fde3
--- /dev/null
+++ b/gas/testsuite/gas/mips/ginv-err.s
@@ -0,0 +1,5 @@
+ .text
+test:
+ ginvi 2
+ ginvt 3,3
+ ginvt $4,4
diff --git a/gas/testsuite/gas/mips/ginv.d b/gas/testsuite/gas/mips/ginv.d
new file mode 100644
index 0000000..411bf6d
--- /dev/null
+++ b/gas/testsuite/gas/mips/ginv.d
@@ -0,0 +1,18 @@
+#objdump: -pdr --prefix-addresses --show-raw-insn
+#name: MIPS GINV
+#as: -mginv -32
+
+# Test GINV instructions
+
+.*: +file format .*mips.*
+#...
+ASEs:
+#...
+ GINV ASE
+#...
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 7c40003d ginvi v0
+[0-9a-f]+ <[^>]*> 7c6000bd ginvt v1,0x0
+[0-9a-f]+ <[^>]*> 7c8001bd ginvt a0,0x1
+ \.\.\.
diff --git a/gas/testsuite/gas/mips/ginv.s b/gas/testsuite/gas/mips/ginv.s
new file mode 100644
index 0000000..63cfb15
--- /dev/null
+++ b/gas/testsuite/gas/mips/ginv.s
@@ -0,0 +1,9 @@
+ .text
+test:
+ ginvi $2
+ ginvt $3,0
+ ginvt $4,1
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 2
+ .space 8
diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp
index 47e923b..786168d 100644
--- a/gas/testsuite/gas/mips/mips.exp
+++ b/gas/testsuite/gas/mips/mips.exp
@@ -2061,4 +2061,7 @@ if { [istarget mips*-*-vxworks*] } {
run_dump_test_arches "crc-err" [mips_arch_list_matching mips32r6]
run_dump_test_arches "crc64" [mips_arch_list_matching mips64r6]
run_dump_test_arches "crc64-err" [mips_arch_list_matching mips64r6]
+
+ run_dump_test_arches "ginv" [mips_arch_list_matching mips32r6]
+ run_dump_test_arches "ginv-err" [mips_arch_list_matching mips32r6]
}
diff --git a/include/elf/mips.h b/include/elf/mips.h
index d11b99f..4e2cde3 100644
--- a/include/elf/mips.h
+++ b/include/elf/mips.h
@@ -1236,7 +1236,9 @@ extern void bfd_mips_elf_swap_abiflags_v0_out
#define AFL_ASE_DSPR3 0x00002000 /* DSP R3 ASE. */
#define AFL_ASE_MIPS16E2 0x00004000 /* MIPS16e2 ASE. */
#define AFL_ASE_CRC 0x00008000 /* CRC ASE. */
-#define AFL_ASE_MASK 0x0000ffff /* All ASEs. */
+#define AFL_ASE_RESERVED1 0x00010000 /* Reserved by MIPS Tech for WIP. */
+#define AFL_ASE_GINV 0x00020000 /* GINV ASE. */
+#define AFL_ASE_MASK 0x0002ffff /* All ASEs. */
/* Values for the isa_ext word of an ABI flags structure. */
diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index fcc70d5..1ab1780 100644
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -989,6 +989,9 @@ mips_opcode_32bit_p (const struct mips_opcode *mo)
"-A" symbolic offset (-262144 .. 262143) << 2 at bit 0
"-B" symbolic offset (-131072 .. 131071) << 3 at bit 0
+ GINV ASE usage:
+ "+\" 2 bit Global TLB invalidate type at bit 8
+
Other:
"()" parens surrounding optional value
"," separates operands
@@ -1003,7 +1006,7 @@ mips_opcode_32bit_p (const struct mips_opcode *mo)
Extension character sequences used so far ("+" followed by the
following), for quick reference when adding more:
"1234567890"
- "~!@#$%^&*|:'";"
+ "~!@#$%^&*|:'";\"
"ABCEFGHIJKLMNOPQRSTUVWXZ"
"abcdefghijklmnopqrstuvwxyz"
@@ -1297,6 +1300,8 @@ static const unsigned int mips_isa_table[] = {
/* Cyclic redundancy check (CRC) ASE. */
#define ASE_CRC 0x00040000
#define ASE_CRC64 0x00080000
+/* Global INValidate Extension. */
+#define ASE_GINV 0x00100000
/* MIPS ISA defines, use instead of hardcoding ISA level. */
diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c
index 95a1937..9a5935b 100644
--- a/opcodes/mips-dis.c
+++ b/opcodes/mips-dis.c
@@ -563,7 +563,7 @@ const struct mips_arch_choice mips_arch_choices[] =
{ "mips32r6", 1, bfd_mach_mipsisa32r6, CPU_MIPS32R6,
ISA_MIPS32R6,
(ASE_EVA | ASE_MSA | ASE_VIRT | ASE_XPA | ASE_MCU | ASE_MT | ASE_DSP
- | ASE_DSPR2 | ASE_DSPR3 | ASE_CRC),
+ | ASE_DSPR2 | ASE_DSPR3 | ASE_CRC | ASE_GINV),
mips_cp0_names_mips3264r2,
mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 },
@@ -603,7 +603,7 @@ const struct mips_arch_choice mips_arch_choices[] =
ISA_MIPS64R6,
(ASE_EVA | ASE_MSA | ASE_MSA64 | ASE_XPA | ASE_VIRT | ASE_VIRT64
| ASE_MCU | ASE_MT | ASE_DSP | ASE_DSPR2 | ASE_DSPR3 | ASE_CRC
- | ASE_CRC64),
+ | ASE_CRC64 | ASE_GINV),
mips_cp0_names_mips3264r2,
mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 },
@@ -901,6 +901,12 @@ set_default_mips_dis_options (struct disassemble_info *info)
static bfd_boolean
parse_mips_ase_option (const char *option)
{
+ if (CONST_STRNEQ (option, "ginv"))
+ {
+ mips_ase |= ASE_GINV;
+ return TRUE;
+ }
+
if (CONST_STRNEQ (option, "msa"))
{
mips_ase |= ASE_MSA;
@@ -2569,6 +2575,10 @@ with the -M switch (multiple options should be separated by commas):\n"));
ASE instructions.\n"));
fprintf (stream, _("\n\
+ ginv Recognize the Global INValidate (GINV) ASe\n\
+ instructions.\n"));
+
+ fprintf (stream, _("\n\
gpr-names=ABI Print GPR names according to specified ABI.\n\
Default: based on binary being disassembled.\n"));
diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index d172801..34088b5 100644
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -139,6 +139,7 @@ decode_mips_operand (const char *p)
case '\'': BRANCH (26, 0, 2);
case '"': BRANCH (21, 0, 2);
case ';': SPECIAL (10, 16, SAME_RS_RT);
+ case '\\': BIT (2, 8, 0); /* (00 .. 11) */
}
break;
@@ -408,6 +409,9 @@ decode_mips_operand (const char *p)
#define CRC ASE_CRC
#define CRC64 ASE_CRC64
+/* Global INValidate (GINV) support. */
+#define GINV ASE_GINV
+
/* The order of overloaded instructions matters. Label arguments and
register arguments look the same. Instructions that can have either
for arguments must apear in the correct order in this table for the
@@ -3361,6 +3365,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"crc32cw", "t,s,-d", 0x7c00018f, 0xfc00ffff, MOD_1|RD_2, 0, 0, CRC, 0 },
{"crc32cd", "t,s,-d", 0x7c0001cf, 0xfc00ffff, MOD_1|RD_2, 0, 0, CRC64, 0 },
+/* MIPS Global INValidate (GINV) ASE. */
+{"ginvi", "s", 0x7c00003d, 0xfc1fffff, RD_1, 0, 0, GINV, 0 },
+{"ginvt", "s,+\\", 0x7c0000bd, 0xfc1ffcff, RD_1, 0, 0, GINV, 0 },
+
/* No hazard protection on coprocessor instructions--they shouldn't
change the state of the processor and if they do it's up to the
user to put in nops as necessary. These are at the end so that the
--
2.7.4