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Re: [PATCH] x86: also optimize zeroing-masking variants of insns
- From: "H.J. Lu" <hjl dot tools at gmail dot com>
- To: Jan Beulich <JBeulich at suse dot com>
- Cc: Binutils <binutils at sourceware dot org>
- Date: Wed, 25 Apr 2018 06:50:34 -0700
- Subject: Re: [PATCH] x86: also optimize zeroing-masking variants of insns
- References: <5AE0735502000078001BE64B@prv1-mh.provo.novell.com>
On Wed, Apr 25, 2018 at 5:23 AM, Jan Beulich <JBeulich@suse.com> wrote:
> When zeroing an element of a register it doesn't matter whether the zero
> results from the actual operation (xor, sub, or nand) or from the
> zeroing-masking taking effect due to a clear mask register bit.
>
> gas/
> 2018-04-25 Jan Beulich <jbeulich@suse.com>
>
> * config/tc-i386.c (optimize_encoding): Check for zeroing
> masking.
> * testsuite/gas/i386/optimize-1.d,
> testsuite/gas/i386/optimize-4.d,
> testsuite/gas/i386/optimize-5.d,
> testsuite/gas/i386/x86-64-optimize-2.d,
> testsuite/gas/i386/x86-64-optimize-5.d,
> testsuite/gas/i386/x86-64-optimize-6.d: Adjust expectations.
>
OK.
Thanks.
--
H.J.