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Re: smaller PLT entries for aarch64 (64-bit ARM)
- From: Andrew Pinski <pinskia at gmail dot com>
- To: John Reiser <jreiser at bitwagon dot com>
- Cc: Binutils <binutils at sourceware dot org>
- Date: Mon, 15 Jan 2018 14:07:39 -0800
- Subject: Re: smaller PLT entries for aarch64 (64-bit ARM)
- Authentication-results: sourceware.org; auth=none
- References: <86e09945-8ca5-e8a6-7f0c-53810d50eb20@bitwagon.com>
On Mon, Jan 15, 2018 at 1:45 PM, John Reiser <jreiser@bitwagon.com> wrote:
> Most of the PLT entries (Program Linkage Table) that I see on aarch64
> (64-bit ARM) contain code like (from binutils-gdb commit origin/master
> e09efd5931daf7eede1f4da46313a1aaadd4dbfa of Mon Jan 8 00:00:33 2018 +0000):
>
> ===== binutils/bfd/elfnn-aarch64.c near line 299
> 0x11, 0x02, 0x40, 0xf9, /* ldr x17, [x16, PLTGOT + n * 8] */
> 0x10, 0x02, 0x00, 0x91, /* add x16, x16, :lo12:PLTGOT + n * 8 */
> =====
>
> but this can be implemented one instruction shorter as:
> 0x11, 0x0e, 0x41, 0xf8, /* ldr x17, [x16, PLTGOT + n * 8]! */
> where the exclamation point '!' denotes a write-back of the entire
> effective address (including the displacement) into the base register.
This change might not help most micro-arc; in fact it can hurt a few
where the load post-update is split and cause extra pipeline bubbles.
The ABI is also fixed, it needs to be 4 instructions (16 bytes) so the
size will not change either.
Thanks,
Andrew
>
> Here is a standalone demonstration that can be single-stepped under gdb:
> ===== gcc -o demo -nostartfiles -nostdlib demo.S
> .globl _start
> _start:
> nop
> sub sp,sp,#4*8
> mov x0,0x1234; str x0,[sp,#0*8]
> mov x0,0x5678; str x0,[sp,#1*8]
> mov x0,0x9abc; str x0,[sp,#2*8]
> mov x0,0xdef0; str x0,[sp,#3*8]
> mov x16,sp
> ldr x17,[x16,#2*8]! // x17 = 0x9abc; x16 += 2*8;
> nop
> =====
>
> --