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Re: [PATCH] x86: correct UDn
>>> On 21.11.17 at 23:12, <hjl.tools@gmail.com> wrote:
> On Mon, Nov 20, 2017 at 5:38 AM, Jan Beulich <JBeulich@suse.com> wrote:
>> --- a/opcodes/i386-opc.tbl
>> +++ b/opcodes/i386-opc.tbl
>> @@ -862,9 +862,12 @@ ud2, 0, 0xf0b, None, 2, Cpu186, No_bSuf|
>> // alias for ud2
>> ud2a, 0, 0xf0b, None, 2, Cpu186, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
>> // 2nd. official undefined instr.
>> -ud1, 0, 0xfb9, None, 2, Cpu186, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
>> +ud1, 2, 0xfb9, None, 2, Cpu186, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 }
>> // alias for ud1
>> -ud2b, 0, 0xfb9, None, 2, Cpu186, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
>> +ud2b, 2, 0xfb9, None, 2, Cpu186, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 }
>> +// 3rd official undefined instr
>> +ud0, 0, 0xfff, None, 2, Cpu186,
> No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
>
> Do we really need this? It will confuse disassembler.
Well, it's officially documented by both Intel and AMD now. And I
don't see why it would confuse the disassembler - neither does
that one use the table here, nor is there anything in it (afaik)
which would special case opcode 0f ff; are you perhaps mixing
this up with opcode ff ff?
>> +ud0, 2, 0xfff, None, 2, CpuSSE4_2, Modrm|No_bSuf|No_sSuf|No_ldSuf, {
> Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|
> Disp32S, Reg16|Reg32|Reg64 }
>
> Where does CpuSSE4_2 come from?
It's the best I could come up with matching XED specifying this as
the variant used from Nehalem onwards.
Jan