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RE: [PATCH 2/6] Enable Intel GFNI instructions

From: "Jan Beulich" <JBeulich at suse dot com>
To: "Igor V Tsimbalist" <igor dot v dot tsimbalist at intel dot com>
Cc: "Hongjiu Lu" <hongjiu dot lu at intel dot com>, "binutils at sourceware dot org" <binutils at sourceware dot org>
Date: Tue, 21 Nov 2017 08:20:32 -0700
Subject: RE: [PATCH 2/6] Enable Intel GFNI instructions
Authentication-results: sourceware.org; auth=none
References: <D511F25789BA7F4EBA64C8A63891A00291F46489@IRSMSX102.ger.corp.intel.com> <5A129B99020000780018FF1F@prv-mh.provo.novell.com> <D511F25789BA7F4EBA64C8A63891A00291F5E912@IRSMSX102.ger.corp.intel.com>

>>> On 21.11.17 at 16:03, <igor.v.tsimbalist@intel.com> wrote:
>>  -----Original Message-----
>> From: Jan Beulich [mailto:JBeulich@suse.com]
>> Sent: Monday, November 20, 2017 9:09 AM
>> To: Tsimbalist, Igor V <igor.v.tsimbalist@intel.com>
>> Cc: Lu, Hongjiu <hongjiu.lu@intel.com>; binutils@sourceware.org 
>> Subject: Re: [PATCH 2/6] Enable Intel GFNI instructions
>> 
>> >>> On 21.10.17 at 11:17, <igor.v.tsimbalist@intel.com> wrote:
>> >+// GFNI + AVX
>> >+
>> >+vgf2p8affineinvqb, 4, 0x66cf, None, 1, CpuAVX|CpuGFNI,
>> Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No
>> _wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8,
>> Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM
>> , RegXMM, RegXMM }
>> >+vgf2p8affineinvqb, 4, 0x66cf, None, 1, CpuAVX|CpuGFNI,
>> Modrm|Vex=2|VexOpcode=2|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|
>> No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8,
>> Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM,
>> RegYMM, RegYMM }
>> >+
>> >+vgf2p8affineqb, 4, 0x66ce, None, 1, CpuAVX|CpuGFNI,
>> Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No
>> _wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8,
>> Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM
>> , RegXMM, RegXMM }
>> >+vgf2p8affineqb, 4, 0x66ce, None, 1, CpuAVX|CpuGFNI,
>> Modrm|Vex=2|VexOpcode=2|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|
>> No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8,
>> Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM,
>> RegYMM, RegYMM }
>> >+
>> >+vgf2p8mulb, 3, 0x66cf, None, 1, CpuAVX|CpuGFNI,
>> Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No
>> _wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {
>> RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S
>> |Vec_Disp8, RegXMM, RegXMM }
>> >+vgf2p8mulb, 3, 0x66cf, None, 1, CpuAVX|CpuGFNI,
>> Modrm|Vex=2|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|
>> No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {
>> RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S
>> |Vec_Disp8, RegYMM, RegYMM }
>> 
>> These being AVX flavors, there shouldn't be any Vec_Disp8 here.
> 
> Attached is a patch to fix this. Ok for trunk?

Same remark as for patch 2.

Jan

References:
- Re: [PATCH 2/6] Enable Intel GFNI instructions
  - From: Jan Beulich
- RE: [PATCH 2/6] Enable Intel GFNI instructions
  - From: Tsimbalist, Igor V

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