This is the mail archive of the
binutils@sourceware.org
mailing list for the binutils project.
[PATCH] x86: fix AVX-512 16-bit addressing
- From: "Jan Beulich" <JBeulich at suse dot com>
- To: <binutils at sourceware dot org>
- Cc: "H.J. Lu" <hjl dot tools at gmail dot com>
- Date: Mon, 20 Nov 2017 08:15:02 -0700
- Subject: [PATCH] x86: fix AVX-512 16-bit addressing
- Authentication-results: sourceware.org; auth=none
Despite EVEX encodings not being available in real and VM86 modes,
16-bit addressing still needs to be handled properly for 16-bit
protected mode as well as 16-bit addressing in 32-bit mode. Neither
should displacements be dropped silently by the assembler, nor should
the disassembler fail to correctly scale 8-bit displacements.
---
I additionally doubt the other CODE_16BIT check (the conditional of
which is visible in patch context here) is correct either; I can't even
figure a way of how this conditional would be reachable in the first
place. Hence I wonder whether that code can be removed altogether.
gas/
2017-11-20 Jan Beulich <jbeulich@suse.com>
* tc-i386.c (check_VecOperands): Don't clear .disp16.
* testsuite/gas/i386/avx512f.s: Add 16-bit addressing tests.
* testsuite/gas/i386/avx512f.d,
testsuite/gas/i386/avx512f-intel.d: Adjust expectations.
opcodes/
2017-11-20 Jan Beulich <jbeulich@suse.com>
* i386-dis.c (OP_E_memory): Also shift the 8-bit immediate in
the 16-bit addressing case.
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -4799,11 +4799,9 @@ check_VecOperands (const insn_template *
else
{
/* Vector insn can only have Vec_Disp8/Disp32 in
- 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
- mode. */
+ 64bit mode, and Vec_Disp8/Disp16/Disp32 in 16/32bit
+ modes. */
i.types[op].bitfield.disp8 = 0;
- if (flag_code != CODE_16BIT)
- i.types[op].bitfield.disp16 = 0;
}
}
else if (flag_code != CODE_16BIT)
--- a/gas/testsuite/gas/i386/avx512f-intel.d
+++ b/gas/testsuite/gas/i386/avx512f-intel.d
@@ -6649,6 +6649,9 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 62 f2 d6 58 27 aa 00 04 00 00 vptestnmq k5,zmm5,QWORD PTR \[edx\+0x400\]\{1to8\}
[ ]*[a-f0-9]+: 62 f2 d6 58 27 6a 80 vptestnmq k5,zmm5,QWORD PTR \[edx-0x400\]\{1to8\}
[ ]*[a-f0-9]+: 62 f2 d6 58 27 aa f8 fb ff ff vptestnmq k5,zmm5,QWORD PTR \[edx-0x408\]\{1to8\}
+[ ]*[a-f0-9]+: 67 62 f1 7c 48 58 07 vaddps zmm0,zmm0,ZMMWORD PTR \[bx\]
+[ ]*[a-f0-9]+: 67 62 f1 7c 48 58 47 01 vaddps zmm0,zmm0,ZMMWORD PTR \[bx\+0x40\]
+[ ]*[a-f0-9]+: 67 62 f1 7c 48 58 87 34 12 vaddps zmm0,zmm0,ZMMWORD PTR \[bx\+0x1234\]
[ ]*[a-f0-9]+: 62 f1 d5 48 58 f4 vaddpd zmm6,zmm5,zmm4
[ ]*[a-f0-9]+: 62 f1 d5 4f 58 f4 vaddpd zmm6\{k7\},zmm5,zmm4
[ ]*[a-f0-9]+: 62 f1 d5 cf 58 f4 vaddpd zmm6\{k7\}\{z\},zmm5,zmm4
@@ -13289,4 +13292,7 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 62 f2 d6 58 27 aa 00 04 00 00 vptestnmq k5,zmm5,QWORD PTR \[edx\+0x400\]\{1to8\}
[ ]*[a-f0-9]+: 62 f2 d6 58 27 6a 80 vptestnmq k5,zmm5,QWORD PTR \[edx-0x400\]\{1to8\}
[ ]*[a-f0-9]+: 62 f2 d6 58 27 aa f8 fb ff ff vptestnmq k5,zmm5,QWORD PTR \[edx-0x408\]\{1to8\}
+[ ]*[a-f0-9]+: 67 62 f1 7c 48 58 07 vaddps zmm0,zmm0,ZMMWORD PTR \[bx\]
+[ ]*[a-f0-9]+: 67 62 f1 7c 48 58 47 01 vaddps zmm0,zmm0,ZMMWORD PTR \[bx\+0x40\]
+[ ]*[a-f0-9]+: 67 62 f1 7c 48 58 87 34 12 vaddps zmm0,zmm0,ZMMWORD PTR \[bx\+0x1234\]
#pass
--- a/gas/testsuite/gas/i386/avx512f.d
+++ b/gas/testsuite/gas/i386/avx512f.d
@@ -6648,6 +6648,9 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 62 f2 d6 58 27 aa 00 04 00 00 vptestnmq 0x400\(%edx\)\{1to8\},%zmm5,%k5
[ ]*[a-f0-9]+: 62 f2 d6 58 27 6a 80 vptestnmq -0x400\(%edx\)\{1to8\},%zmm5,%k5
[ ]*[a-f0-9]+: 62 f2 d6 58 27 aa f8 fb ff ff vptestnmq -0x408\(%edx\)\{1to8\},%zmm5,%k5
+[ ]*[a-f0-9]+: 67 62 f1 7c 48 58 07 vaddps \(%bx\),%zmm0,%zmm0
+[ ]*[a-f0-9]+: 67 62 f1 7c 48 58 47 01 vaddps 0x40\(%bx\),%zmm0,%zmm0
+[ ]*[a-f0-9]+: 67 62 f1 7c 48 58 87 34 12 vaddps 0x1234\(%bx\),%zmm0,%zmm0
[ ]*[a-f0-9]+: 62 f1 d5 48 58 f4 vaddpd %zmm4,%zmm5,%zmm6
[ ]*[a-f0-9]+: 62 f1 d5 4f 58 f4 vaddpd %zmm4,%zmm5,%zmm6\{%k7\}
[ ]*[a-f0-9]+: 62 f1 d5 cf 58 f4 vaddpd %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
@@ -13288,4 +13291,7 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 62 f2 d6 58 27 aa 00 04 00 00 vptestnmq 0x400\(%edx\)\{1to8\},%zmm5,%k5
[ ]*[a-f0-9]+: 62 f2 d6 58 27 6a 80 vptestnmq -0x400\(%edx\)\{1to8\},%zmm5,%k5
[ ]*[a-f0-9]+: 62 f2 d6 58 27 aa f8 fb ff ff vptestnmq -0x408\(%edx\)\{1to8\},%zmm5,%k5
+[ ]*[a-f0-9]+: 67 62 f1 7c 48 58 07 vaddps \(%bx\),%zmm0,%zmm0
+[ ]*[a-f0-9]+: 67 62 f1 7c 48 58 47 01 vaddps 0x40\(%bx\),%zmm0,%zmm0
+[ ]*[a-f0-9]+: 67 62 f1 7c 48 58 87 34 12 vaddps 0x1234\(%bx\),%zmm0,%zmm0
#pass
--- a/gas/testsuite/gas/i386/avx512f.s
+++ b/gas/testsuite/gas/i386/avx512f.s
@@ -7262,6 +7262,10 @@ _start:
vptestnmq -1024(%edx){1to8}, %zmm5, %k5 # AVX512F Disp8
vptestnmq -1032(%edx){1to8}, %zmm5, %k5 # AVX512F
+ vaddps (%bx), %zmm0, %zmm0
+ vaddps 0x40(%bx), %zmm0, %zmm0
+ vaddps 0x1234(%bx), %zmm0, %zmm0
+
.intel_syntax noprefix
vaddpd zmm6, zmm5, zmm4 # AVX512F
vaddpd zmm6{k7}, zmm5, zmm4 # AVX512F
@@ -14520,3 +14524,7 @@ _start:
vptestnmq k5, zmm5, [edx+1024]{1to8} # AVX512F
vptestnmq k5, zmm5, [edx-1024]{1to8} # AVX512F Disp8
vptestnmq k5, zmm5, [edx-1032]{1to8} # AVX512F
+
+ vaddps zmm0, zmm0, [bx]
+ vaddps zmm0, zmm0, [bx+0x40]
+ vaddps zmm0, zmm0, [bx+0x1234]
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -15481,6 +15481,8 @@ OP_E_memory (int bytemode, int sizeflag)
disp = *codep++;
if ((disp & 0x80) != 0)
disp -= 0x100;
+ if (vex.evex && shift > 0)
+ disp <<= shift;
break;
case 2:
disp = get16 ();