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Re: [PATCH v2] x86-64: don't allow use of %axl as accumulator


On Tue, Nov 14, 2017 at 12:17 AM, Jan Beulich <JBeulich@suse.com> wrote:
> Just like %cxl can't be used as shift count register. Otherwise for
> consistency %cxl would need to gain "ShiftCount" and use of both ought
> to properly cause REX prefixes to be emitted.
> ---
> v2: Extend new testcase.
>
> gas/
> 2017-11-14  Jan Beulich  <jbeulich@suse.com>
>
>         * testsuite/gas/i386/x86-64-reg-bad.{s,l}: New.
>         * testsuite/gas/i386/i386.exp: Run new test.
>
> opcodes/
> 2017-11-14  Jan Beulich  <jbeulich@suse.com>
>
>         * i386-reg.tbl (axl): Remove Acc and Byte.
>         * i386-tbl.h: Re-generate.
>
> --- 2017-11-10/gas/testsuite/gas/i386/i386.exp
> +++ 2017-11-10/gas/testsuite/gas/i386/i386.exp
> @@ -628,6 +628,7 @@ if [expr ([istarget "i*86-*-*"] || [ista
>      run_dump_test "x86-64-mem"
>      run_dump_test "x86-64-mem-intel"
>      run_dump_test "x86-64-reg"
> +    run_list_test "x86-64-reg-bad" "-al"
>      run_dump_test "x86-64-reg-intel"
>      run_dump_test "x86-64-sib"
>      run_dump_test "x86-64-sib-intel"
> --- 2017-11-10/gas/testsuite/gas/i386/x86-64-reg-bad.l
> +++ 2017-11-10/gas/testsuite/gas/i386/x86-64-reg-bad.l
> @@ -0,0 +1,27 @@
> +.*: Assembler messages:
> +.*:5: Error: .* mismatch for `movabs'
> +.*:14: Error: .* mismatch for `div'
> +.*:15: Error: .* mismatch for `in'
> +.*:16: Error: .* mismatch for `lods'
> +.*:17: Error: .* mismatch for `shl'
> +GAS LISTING .*
> +
> +
> +[      ]*[1-9][0-9]*[  ]+\# Check %axl / %cxl aren't permitted as accumulator / shift count, but
> +[      ]*[1-9][0-9]*[  ]+\# make sure any of the extended low registers still work as intended
> +[      ]*[1-9][0-9]*[  ]+\.text
> +[      ]*[1-9][0-9]*[  ]+reg:
> +[      ]*[1-9][0-9]*[  ]+movabs        -1, %axl
> +[      ]*[1-9][0-9]*[  ]+\?* 4080C001[         ]+add   \$1, %axl
> +[      ]*[1-9][0-9]*[  ]+\?* 4080C101[         ]+add   \$1, %cxl
> +[      ]*[1-9][0-9]*[  ]+\?* 4080C201[         ]+add   \$1, %dxl
> +[      ]*[1-9][0-9]*[  ]+\?* 4080C301[         ]+add   \$1, %bxl
> +[      ]*[1-9][0-9]*[  ]+\?* 4080C401[         ]+add   \$1, %spl
> +[      ]*[1-9][0-9]*[  ]+\?* 4080C501[         ]+add   \$1, %bpl
> +[      ]*[1-9][0-9]*[  ]+\?* 4080C601[         ]+add   \$1, %sil
> +[      ]*[1-9][0-9]*[  ]+\?* 4080C701[         ]+add   \$1, %dil
> +[      ]*[1-9][0-9]*[  ]+div   %bl, %axl
> +[      ]*[1-9][0-9]*[  ]+in    %dx, %axl
> +[      ]*[1-9][0-9]*[  ]+lods  \(%rsi\), %axl
> +[      ]*[1-9][0-9]*[  ]+shl   %cxl, %eax
> +[      ]*[1-9][0-9]*[  ]+\?* 40F6C001[         ]+test  \$1, %axl
> --- 2017-11-10/gas/testsuite/gas/i386/x86-64-reg-bad.s
> +++ 2017-11-10/gas/testsuite/gas/i386/x86-64-reg-bad.s
> @@ -0,0 +1,18 @@
> +# Check %axl / %cxl aren't permitted as accumulator / shift count, but
> +# make sure any of the extended low registers still work as intended
> +       .text
> +reg:
> +       movabs  -1, %axl
> +       add     $1, %axl
> +       add     $1, %cxl
> +       add     $1, %dxl
> +       add     $1, %bxl
> +       add     $1, %spl
> +       add     $1, %bpl
> +       add     $1, %sil
> +       add     $1, %dil

Please move

+       add     $1, %axl
+       add     $1, %cxl
+       add     $1, %dxl
+       add     $1, %bxl
+       add     $1, %spl
+       add     $1, %bpl
+       add     $1, %sil
+       add     $1, %dil

to x86-64-specific-reg.s.   OK with that change.

Thanks for your patience.

> +       div     %bl, %axl
> +       in      %dx, %axl
> +       lods    (%rsi), %axl
> +       shl     %cxl, %eax
> +       test    $1, %axl
> --- 2017-11-10/opcodes/i386-reg.tbl
> +++ 2017-11-10/opcodes/i386-reg.tbl
> @@ -29,7 +29,7 @@ ah, Reg8, 0, 4, Dw2Inval, Dw2Inval
>  ch, Reg8, 0, 5, Dw2Inval, Dw2Inval
>  dh, Reg8, 0, 6, Dw2Inval, Dw2Inval
>  bh, Reg8, 0, 7, Dw2Inval, Dw2Inval
> -axl, Reg8|Acc|Byte, RegRex64, 0, Dw2Inval, Dw2Inval
> +axl, Reg8, RegRex64, 0, Dw2Inval, Dw2Inval
>  cxl, Reg8, RegRex64, 1, Dw2Inval, Dw2Inval
>  dxl, Reg8, RegRex64, 2, Dw2Inval, Dw2Inval
>  bxl, Reg8, RegRex64, 3, Dw2Inval, Dw2Inval
>
>
>



-- 
H.J.


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