Re: [PATCH] x86: ignore high register select bit(s) in 32- and 16-bit modes

["H.J. Lu" <hjl dot tools at gmail dot com>]

On Tue, Feb 28, 2017 at 1:51 AM, Jan Beulich <JBeulich@suse.com> wrote:
>>>> On 24.02.17 at 17:57, <hjl.tools@gmail.com> wrote:
>> On Tue, Feb 21, 2017 at 8:27 AM, Jan Beulich <JBeulich@suse.com> wrote:
>>> While commits 9889cbb14e ("Check invalid mask registers") and
>>> abfcb414b9 ("X86: Ignore REX_B bit for 32-bit XOP instructions") went a
>>> bit into the right direction, this wasn't quite enough:
>>> - VEX.vvvv has its high bit ignored
>>> - EVEX.vvvv has its high bit ignored together with EVEX.v'
>>> - the high bits of {,E}VEX.vvvv should not be prematurely zapped, to
>>>   allow proper checking of them when the fields has to hold al ones
>>> - when the high bits of an immediate specify a register, bit 7 is
>>>   ignored
>>> - GPR names should be determined base on REX_W rather than vex.w
>>>
>>
>> There are several issues.  Please send individual patches to address
>> them separately. Remove VEXI4_Fixup should be in a separate patch.
>
> I disagree (there's just one fundamental issue, requiring fixes in
> multiple places). At best the 3rd of the five items above could be
> viewed as a separate issue imo. But anyway, it may be several
> months until I may find time to split this up.
>

At minimum, I'd like to see 32-bit GPR change, remove VEXI4_Fixup
and the rest.  We are in no hurry for these.


-- 
H.J.