[PATCH v2][ARM] Fix the decoding of indexed element VCMLA instruction

[Szabolcs Nagy <szabolcs dot nagy at arm dot com>]

On 16/01/17 11:11, Jan Beulich wrote:
>>>> On 16.01.17 at 11:56, <nickc@redhat.com> wrote:
>>> opcodes/
>>> 2017-01-13  Szabolcs Nagy  <szabolcs.nagy@arm.com>
>>>
>>> 	* arm-dis.c (coprocessor_opcodes): Fix vcmla mask.
>>
>> Approved - please apply.
> 
> I'm sorry for having noticed only over the weekend, but I think
> there's a second issue here: Aiui the instruction takes a 1-bit
> immediate (selecting between 90° and 270°), yet doesn't
> decode bit 20 (which would be required to always be 1 for only
> those two value to be selectable). It is of no help that the test
> case only ever tests #90 as the immediate operand.

vcadd immediate is 90/270, encoded in bit 24.
vcmla immediate is 0/90/180/270, encoded in bits 23-24
indexed element vcmla immediate is 0/90/180/270, in bits 20-21.

there was a bug in the immediate decoding of indexed element
vcmla, i assume that's what you've seen, i think i'll propose
a separate patch to make the disasm format string cleaner
(i'm not yet sure if it will be a new format char or some other
way, but my current hack is clearly error prone).

v2: fix rotation immediates, add more test coverage.


Bit 24 of the indexed element vcmla decode mask was incorrectly
left unset.  This could cause incorrect disassembly of some
currently undefined instructions as vcmla.

Rotatation immediates were not printed correctly in the disassembly
(could print 170 and 280 instead of 180 and 270).

opcodes/
2017-01-17  Szabolcs Nagy  <szabolcs.nagy@arm.com>

	* arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.

gas/
2017-01-17  Szabolcs Nagy  <szabolcs.nagy@arm.com>

	* testsuite/gas/arm/armv8_3-a-simd.s: Add vcmla tests.
	* testsuite/gas/arm/armv8_3-a-simd.d: Update.

diff --git a/gas/testsuite/gas/arm/armv8_3-a-simd.d b/gas/testsuite/gas/arm/armv8_3-a-simd.d
index c420cffd87e67c163d79f474c4ec1089e8b642bd..356b5a643e75dc71136f06ad53f4b7fd12a2ffd1 100644
--- a/gas/testsuite/gas/arm/armv8_3-a-simd.d
+++ b/gas/testsuite/gas/arm/armv8_3-a-simd.d
@@ -25,6 +25,12 @@ Disassembly of section .text:
  +[0-9a-f]+:	fe142863 	vcmla.f16	q1, q2, d3\[1\], #90
  +[0-9a-f]+:	fed658a7 	vcmla.f32	d21, d22, d23\[0\], #90
  +[0-9a-f]+:	fe942867 	vcmla.f32	q1, q2, d23\[0\], #90
+ +[0-9a-f]+:	fe042863 	vcmla.f16	q1, q2, d3\[1\], #0
+ +[0-9a-f]+:	fe242863 	vcmla.f16	q1, q2, d3\[1\], #180
+ +[0-9a-f]+:	fe342863 	vcmla.f16	q1, q2, d3\[1\], #270
+ +[0-9a-f]+:	fe842843 	vcmla.f32	q1, q2, d3\[0\], #0
+ +[0-9a-f]+:	fea42843 	vcmla.f32	q1, q2, d3\[0\], #180
+ +[0-9a-f]+:	feb42843 	vcmla.f32	q1, q2, d3\[0\], #270
 
 [0-9a-f]+ <.*>:
  +[0-9a-f]+:	fc94 2846 	vcadd.f32	q1, q2, q3, #90
@@ -45,3 +51,9 @@ Disassembly of section .text:
  +[0-9a-f]+:	fe14 2863 	vcmla.f16	q1, q2, d3\[1\], #90
  +[0-9a-f]+:	fed6 58a7 	vcmla.f32	d21, d22, d23\[0\], #90
  +[0-9a-f]+:	fe94 2867 	vcmla.f32	q1, q2, d23\[0\], #90
+ +[0-9a-f]+:	fe04 2863 	vcmla.f16	q1, q2, d3\[1\], #0
+ +[0-9a-f]+:	fe24 2863 	vcmla.f16	q1, q2, d3\[1\], #180
+ +[0-9a-f]+:	fe34 2863 	vcmla.f16	q1, q2, d3\[1\], #270
+ +[0-9a-f]+:	fe84 2843 	vcmla.f32	q1, q2, d3\[0\], #0
+ +[0-9a-f]+:	fea4 2843 	vcmla.f32	q1, q2, d3\[0\], #180
+ +[0-9a-f]+:	feb4 2843 	vcmla.f32	q1, q2, d3\[0\], #270
diff --git a/gas/testsuite/gas/arm/armv8_3-a-simd.s b/gas/testsuite/gas/arm/armv8_3-a-simd.s
index fde2f7632b12cb711918d529dc5f9c602874c22c..4ff5817a304087975174b9d6691e8cff7baf65a3 100644
--- a/gas/testsuite/gas/arm/armv8_3-a-simd.s
+++ b/gas/testsuite/gas/arm/armv8_3-a-simd.s
@@ -24,6 +24,13 @@ A1:
 	vcmla.f32 d21,d22,d23[0],#90
 	vcmla.f32 q1,q2,d23[0],#90
 
+	vcmla.f16 q1,q2,d3[1],#0
+	vcmla.f16 q1,q2,d3[1],#180
+	vcmla.f16 q1,q2,d3[1],#270
+	vcmla.f32 q1,q2,d3[0],#0
+	vcmla.f32 q1,q2,d3[0],#180
+	vcmla.f32 q1,q2,d3[0],#270
+
 T1:
 	.thumb
 
@@ -47,3 +54,10 @@ T1:
 	vcmla.f16 q1,q2,d3[1],#90
 	vcmla.f32 d21,d22,d23[0],#90
 	vcmla.f32 q1,q2,d23[0],#90
+
+	vcmla.f16 q1,q2,d3[1],#0
+	vcmla.f16 q1,q2,d3[1],#180
+	vcmla.f16 q1,q2,d3[1],#270
+	vcmla.f32 q1,q2,d3[0],#0
+	vcmla.f32 q1,q2,d3[0],#180
+	vcmla.f32 q1,q2,d3[0],#270
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index 167c6685c5ce24e2c2e4e8c46e8c5a92aa025c9f..2987403fbfae14b4551e472ed12537adf95a5316 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -897,13 +897,13 @@ static const struct opcode32 coprocessor_opcodes[] =
   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
     0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
-    0xfe000800, 0xfea00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"},
+    0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"},
   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
-    0xfe200800, 0xfea00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%23?780"},
+    0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%20?780"},
   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
-    0xfe800800, 0xfea00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"},
+    0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"},
   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
-    0xfea00800, 0xfea00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%23?780"},
+    0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%20?780"},
 
   /* V5 coprocessor instructions.  */
   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),