RISC-V Fixes for 2.28 v2

[Palmer Dabbelt <palmer at dabbelt dot com>]

Thanks to everyone who reviewed our patches.  I believe I've taken everyone's
feedback into account.  The issues were fairly small, so unless there's any
more feedback I think this should be ready to go.

Here's something that I hope is actually a set of ChangeLog entries this time,
as opposed to whatever I did last time.



opcodes/ChangeLog

2016-12-17 Andrew Waterman <andrew@sifive.com>

	* riscv-opc.c: Correct assembler mnemonic for aqrl AMOs.

2016-12-17 Andrew Waterman <andrew@sifive.com>

	* riscv-opc.c: Fix disassembly of CSR instructions under -Mno-aliases.

2016-12-17 Andrew Waterman <andrew@sifive.com>

	* riscv-opc.c: Add canonical JALR assembly representation.

2016-12-17 Andrew Waterman <andrew@sifive.com>

	* riscv-dis.c: Re-work RISC-V gas flags: now we just support -mabi and
	-march.



gas/ChangeLog

2016-12-17 Andrew Waterman <andrew@sifive.com>

	* config/tc-riscv.c: Don't define our own .p2align.
	* config/tc-riscv.h: Likewise.

2016-12-17 Andrew Waterman <andrew@sifive.com>

	* config/tc-riscv.c: Re-work RISC-V gas flags: now we just support
	-mabi and -march.

	* config/tc-riscv.h: Likewise.
	* doc/as.texinfo: Document -mabi and -march.
	* doc/c-riscv.texi: Likewise.

2016-12-17 Andrew Waterman <andrew@sifive.com>
	   Kuan-Lin Chen <kuanlinchentw@gmail.com>

	* config/tc-riscv.c: Likewise.
	* config/tc-riscv.h: F registers might be 4-type aligned, so always
	specify DWARF2_CIE_DATA_ALIGNMENT is 4.



bfd/ChangeLog

2016-12-17 Andrew Waterman <andrew@sifive.com>

	* elfnn-riscv.c: 

2016-12-17 Andrew Waterman <andrew@sifive.com>

	* elfnn-riscv.c: Fix an integer overflow in relocation handling.

2016-12-17 Andrew Waterman <andrew@sifive.com>

	* elfnn-riscv.c: Formatting changes for RISC-V.
	* elfxx-riscv.c: Likewise.

2016-12-17 Andrew Waterman <andrew@sifive.com>
	   Kuan-Lin Chen <kuanlinchentw@gmail.com>

	* bfd-in2.h: Define some new relocations, needed to support CFI
	relaxation: TPREL_I, TPREL_S, RELAX, SUB6, SET6, SET8, SET16, SET32.
	* elfnn-riscv.c: Implement these new relocations
	* elfxx-riscv.c: Likewise.
	* libbfd.h: Likewise.
	* reloc.c: Likewise.

2016-12-17 Palmer Dabbelt <palmer@dabbelt.com>

	* elfnn-riscv.c: Improve a LD error message when linking elf32 and
	elf64.