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[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
- From: Matthew Wahab <matthew dot wahab at foss dot arm dot com>
- To: binutils at sourceware dot org
- Date: Fri, 11 Dec 2015 12:03:35 +0000
- Subject: [AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
- Authentication-results: sourceware.org; auth=none
- References: <566AB800 dot 1090308 at foss dot arm dot com>
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.
Ok for trunk?
Matthew
gas/testsuite/
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
>From 58ab2235c20bfcaa68e75ef4f8dd7c9c2df04f39 Mon Sep 17 00:00:00 2001
From: Matthew Wahab <matthew.wahab@arm.com>
Date: Thu, 10 Sep 2015 13:00:41 +0100
Subject: [PATCH 04/14] [AArch64] Add FP16 vector two-register misc.
instructions (III).
---
gas/testsuite/gas/aarch64/advsimd-fp16.d | 145 ++
gas/testsuite/gas/aarch64/advsimd-fp16.s | 55 +
gas/testsuite/gas/aarch64/verbose-error.l | 5 +-
opcodes/aarch64-asm-2.c | 660 +++---
opcodes/aarch64-dis-2.c | 3107 ++++++++++++++++-------------
opcodes/aarch64-opc-2.c | 112 +-
opcodes/aarch64-tbl.h | 65 +
7 files changed, 2366 insertions(+), 1783 deletions(-)
diff --git a/gas/testsuite/gas/aarch64/advsimd-fp16.d b/gas/testsuite/gas/aarch64/advsimd-fp16.d
index 5814bec..b2a24ad 100644
--- a/gas/testsuite/gas/aarch64/advsimd-fp16.d
+++ b/gas/testsuite/gas/aarch64/advsimd-fp16.d
@@ -203,3 +203,148 @@ Disassembly of section \.text:
[0-9a-f]+: 5ea2fc20 frsqrts s0, s1, s2
[0-9a-f]+: 5ec23c20 frsqrts h0, h1, h2
[0-9a-f]+: 5ec03c00 frsqrts h0, h0, h0
+ [0-9a-f]+: 4ee0c820 fcmgt v0.2d, v1.2d, #0.0
+ [0-9a-f]+: 0ea0c820 fcmgt v0.2s, v1.2s, #0.0
+ [0-9a-f]+: 4ea0c820 fcmgt v0.4s, v1.4s, #0.0
+ [0-9a-f]+: 0ef8c820 fcmgt v0.4h, v1.4h, #0.0
+ [0-9a-f]+: 4ef8c820 fcmgt v0.8h, v1.8h, #0.0
+ [0-9a-f]+: 6ee0c820 fcmge v0.2d, v1.2d, #0.0
+ [0-9a-f]+: 2ea0c820 fcmge v0.2s, v1.2s, #0.0
+ [0-9a-f]+: 6ea0c820 fcmge v0.4s, v1.4s, #0.0
+ [0-9a-f]+: 2ef8c820 fcmge v0.4h, v1.4h, #0.0
+ [0-9a-f]+: 6ef8c820 fcmge v0.8h, v1.8h, #0.0
+ [0-9a-f]+: 4ee0d820 fcmeq v0.2d, v1.2d, #0.0
+ [0-9a-f]+: 0ea0d820 fcmeq v0.2s, v1.2s, #0.0
+ [0-9a-f]+: 4ea0d820 fcmeq v0.4s, v1.4s, #0.0
+ [0-9a-f]+: 0ef8d820 fcmeq v0.4h, v1.4h, #0.0
+ [0-9a-f]+: 4ef8d820 fcmeq v0.8h, v1.8h, #0.0
+ [0-9a-f]+: 6ee0d820 fcmle v0.2d, v1.2d, #0.0
+ [0-9a-f]+: 2ea0d820 fcmle v0.2s, v1.2s, #0.0
+ [0-9a-f]+: 6ea0d820 fcmle v0.4s, v1.4s, #0.0
+ [0-9a-f]+: 2ef8d820 fcmle v0.4h, v1.4h, #0.0
+ [0-9a-f]+: 6ef8d820 fcmle v0.8h, v1.8h, #0.0
+ [0-9a-f]+: 4ee0e820 fcmlt v0.2d, v1.2d, #0.0
+ [0-9a-f]+: 0ea0e820 fcmlt v0.2s, v1.2s, #0.0
+ [0-9a-f]+: 4ea0e820 fcmlt v0.4s, v1.4s, #0.0
+ [0-9a-f]+: 0ef8e820 fcmlt v0.4h, v1.4h, #0.0
+ [0-9a-f]+: 4ef8e820 fcmlt v0.8h, v1.8h, #0.0
+ [0-9a-f]+: 4ee0f820 fabs v0.2d, v1.2d
+ [0-9a-f]+: 0ea0f820 fabs v0.2s, v1.2s
+ [0-9a-f]+: 4ea0f820 fabs v0.4s, v1.4s
+ [0-9a-f]+: 0ef8f820 fabs v0.4h, v1.4h
+ [0-9a-f]+: 4ef8f820 fabs v0.8h, v1.8h
+ [0-9a-f]+: 6ee0f820 fneg v0.2d, v1.2d
+ [0-9a-f]+: 2ea0f820 fneg v0.2s, v1.2s
+ [0-9a-f]+: 6ea0f820 fneg v0.4s, v1.4s
+ [0-9a-f]+: 2ef8f820 fneg v0.4h, v1.4h
+ [0-9a-f]+: 6ef8f820 fneg v0.8h, v1.8h
+ [0-9a-f]+: 4e618820 frintn v0.2d, v1.2d
+ [0-9a-f]+: 0e218820 frintn v0.2s, v1.2s
+ [0-9a-f]+: 4e218820 frintn v0.4s, v1.4s
+ [0-9a-f]+: 0e798820 frintn v0.4h, v1.4h
+ [0-9a-f]+: 4e798820 frintn v0.8h, v1.8h
+ [0-9a-f]+: 6e618820 frinta v0.2d, v1.2d
+ [0-9a-f]+: 2e218820 frinta v0.2s, v1.2s
+ [0-9a-f]+: 6e218820 frinta v0.4s, v1.4s
+ [0-9a-f]+: 2e798820 frinta v0.4h, v1.4h
+ [0-9a-f]+: 6e798820 frinta v0.8h, v1.8h
+ [0-9a-f]+: 4ee18820 frintp v0.2d, v1.2d
+ [0-9a-f]+: 0ea18820 frintp v0.2s, v1.2s
+ [0-9a-f]+: 4ea18820 frintp v0.4s, v1.4s
+ [0-9a-f]+: 0ef98820 frintp v0.4h, v1.4h
+ [0-9a-f]+: 4ef98820 frintp v0.8h, v1.8h
+ [0-9a-f]+: 4e619820 frintm v0.2d, v1.2d
+ [0-9a-f]+: 0e219820 frintm v0.2s, v1.2s
+ [0-9a-f]+: 4e219820 frintm v0.4s, v1.4s
+ [0-9a-f]+: 0e799820 frintm v0.4h, v1.4h
+ [0-9a-f]+: 4e799820 frintm v0.8h, v1.8h
+ [0-9a-f]+: 6e619820 frintx v0.2d, v1.2d
+ [0-9a-f]+: 2e219820 frintx v0.2s, v1.2s
+ [0-9a-f]+: 6e219820 frintx v0.4s, v1.4s
+ [0-9a-f]+: 2e799820 frintx v0.4h, v1.4h
+ [0-9a-f]+: 6e799820 frintx v0.8h, v1.8h
+ [0-9a-f]+: 4ee19820 frintz v0.2d, v1.2d
+ [0-9a-f]+: 0ea19820 frintz v0.2s, v1.2s
+ [0-9a-f]+: 4ea19820 frintz v0.4s, v1.4s
+ [0-9a-f]+: 0ef99820 frintz v0.4h, v1.4h
+ [0-9a-f]+: 4ef99820 frintz v0.8h, v1.8h
+ [0-9a-f]+: 6ee19820 frinti v0.2d, v1.2d
+ [0-9a-f]+: 2ea19820 frinti v0.2s, v1.2s
+ [0-9a-f]+: 6ea19820 frinti v0.4s, v1.4s
+ [0-9a-f]+: 2ef99820 frinti v0.4h, v1.4h
+ [0-9a-f]+: 6ef99820 frinti v0.8h, v1.8h
+ [0-9a-f]+: 4e61a820 fcvtns v0.2d, v1.2d
+ [0-9a-f]+: 0e21a820 fcvtns v0.2s, v1.2s
+ [0-9a-f]+: 4e21a820 fcvtns v0.4s, v1.4s
+ [0-9a-f]+: 0e79a820 fcvtns v0.4h, v1.4h
+ [0-9a-f]+: 4e79a820 fcvtns v0.8h, v1.8h
+ [0-9a-f]+: 6e61a820 fcvtnu v0.2d, v1.2d
+ [0-9a-f]+: 2e21a820 fcvtnu v0.2s, v1.2s
+ [0-9a-f]+: 6e21a820 fcvtnu v0.4s, v1.4s
+ [0-9a-f]+: 2e79a820 fcvtnu v0.4h, v1.4h
+ [0-9a-f]+: 6e79a820 fcvtnu v0.8h, v1.8h
+ [0-9a-f]+: 4ee1a820 fcvtps v0.2d, v1.2d
+ [0-9a-f]+: 0ea1a820 fcvtps v0.2s, v1.2s
+ [0-9a-f]+: 4ea1a820 fcvtps v0.4s, v1.4s
+ [0-9a-f]+: 0ef9a820 fcvtps v0.4h, v1.4h
+ [0-9a-f]+: 4ef9a820 fcvtps v0.8h, v1.8h
+ [0-9a-f]+: 6ee1a820 fcvtpu v0.2d, v1.2d
+ [0-9a-f]+: 2ea1a820 fcvtpu v0.2s, v1.2s
+ [0-9a-f]+: 6ea1a820 fcvtpu v0.4s, v1.4s
+ [0-9a-f]+: 2ef9a820 fcvtpu v0.4h, v1.4h
+ [0-9a-f]+: 6ef9a820 fcvtpu v0.8h, v1.8h
+ [0-9a-f]+: 4e61b820 fcvtms v0.2d, v1.2d
+ [0-9a-f]+: 0e21b820 fcvtms v0.2s, v1.2s
+ [0-9a-f]+: 4e21b820 fcvtms v0.4s, v1.4s
+ [0-9a-f]+: 0e79b820 fcvtms v0.4h, v1.4h
+ [0-9a-f]+: 4e79b820 fcvtms v0.8h, v1.8h
+ [0-9a-f]+: 6e61b820 fcvtmu v0.2d, v1.2d
+ [0-9a-f]+: 2e21b820 fcvtmu v0.2s, v1.2s
+ [0-9a-f]+: 6e21b820 fcvtmu v0.4s, v1.4s
+ [0-9a-f]+: 2e79b820 fcvtmu v0.4h, v1.4h
+ [0-9a-f]+: 6e79b820 fcvtmu v0.8h, v1.8h
+ [0-9a-f]+: 4ee1b820 fcvtzs v0.2d, v1.2d
+ [0-9a-f]+: 0ea1b820 fcvtzs v0.2s, v1.2s
+ [0-9a-f]+: 4ea1b820 fcvtzs v0.4s, v1.4s
+ [0-9a-f]+: 0ef9b820 fcvtzs v0.4h, v1.4h
+ [0-9a-f]+: 4ef9b820 fcvtzs v0.8h, v1.8h
+ [0-9a-f]+: 6ee1b820 fcvtzu v0.2d, v1.2d
+ [0-9a-f]+: 2ea1b820 fcvtzu v0.2s, v1.2s
+ [0-9a-f]+: 6ea1b820 fcvtzu v0.4s, v1.4s
+ [0-9a-f]+: 2ef9b820 fcvtzu v0.4h, v1.4h
+ [0-9a-f]+: 6ef9b820 fcvtzu v0.8h, v1.8h
+ [0-9a-f]+: 4e61c820 fcvtas v0.2d, v1.2d
+ [0-9a-f]+: 0e21c820 fcvtas v0.2s, v1.2s
+ [0-9a-f]+: 4e21c820 fcvtas v0.4s, v1.4s
+ [0-9a-f]+: 0e79c820 fcvtas v0.4h, v1.4h
+ [0-9a-f]+: 4e79c820 fcvtas v0.8h, v1.8h
+ [0-9a-f]+: 6e61c820 fcvtau v0.2d, v1.2d
+ [0-9a-f]+: 2e21c820 fcvtau v0.2s, v1.2s
+ [0-9a-f]+: 6e21c820 fcvtau v0.4s, v1.4s
+ [0-9a-f]+: 2e79c820 fcvtau v0.4h, v1.4h
+ [0-9a-f]+: 6e79c820 fcvtau v0.8h, v1.8h
+ [0-9a-f]+: 4e61d820 scvtf v0.2d, v1.2d
+ [0-9a-f]+: 0e21d820 scvtf v0.2s, v1.2s
+ [0-9a-f]+: 4e21d820 scvtf v0.4s, v1.4s
+ [0-9a-f]+: 0e79d820 scvtf v0.4h, v1.4h
+ [0-9a-f]+: 4e79d820 scvtf v0.8h, v1.8h
+ [0-9a-f]+: 6e61d820 ucvtf v0.2d, v1.2d
+ [0-9a-f]+: 2e21d820 ucvtf v0.2s, v1.2s
+ [0-9a-f]+: 6e21d820 ucvtf v0.4s, v1.4s
+ [0-9a-f]+: 2e79d820 ucvtf v0.4h, v1.4h
+ [0-9a-f]+: 6e79d820 ucvtf v0.8h, v1.8h
+ [0-9a-f]+: 4ee1d820 frecpe v0.2d, v1.2d
+ [0-9a-f]+: 0ea1d820 frecpe v0.2s, v1.2s
+ [0-9a-f]+: 4ea1d820 frecpe v0.4s, v1.4s
+ [0-9a-f]+: 0ef9d820 frecpe v0.4h, v1.4h
+ [0-9a-f]+: 4ef9d820 frecpe v0.8h, v1.8h
+ [0-9a-f]+: 6ee1d820 frsqrte v0.2d, v1.2d
+ [0-9a-f]+: 2ea1d820 frsqrte v0.2s, v1.2s
+ [0-9a-f]+: 6ea1d820 frsqrte v0.4s, v1.4s
+ [0-9a-f]+: 2ef9d820 frsqrte v0.4h, v1.4h
+ [0-9a-f]+: 6ef9d820 frsqrte v0.8h, v1.8h
+ [0-9a-f]+: 6ee1f820 fsqrt v0.2d, v1.2d
+ [0-9a-f]+: 2ea1f820 fsqrt v0.2s, v1.2s
+ [0-9a-f]+: 6ea1f820 fsqrt v0.4s, v1.4s
+ [0-9a-f]+: 2ef9f820 fsqrt v0.4h, v1.4h
+ [0-9a-f]+: 6ef9f820 fsqrt v0.8h, v1.8h
diff --git a/gas/testsuite/gas/aarch64/advsimd-fp16.s b/gas/testsuite/gas/aarch64/advsimd-fp16.s
index 99f27f2..3f3cafb 100644
--- a/gas/testsuite/gas/aarch64/advsimd-fp16.s
+++ b/gas/testsuite/gas/aarch64/advsimd-fp16.s
@@ -57,3 +57,58 @@
sthree_same facgt
sthree_same frecps
sthree_same frsqrts
+
+ /* Vector two-register misc. */
+
+ .macro tworeg_zero, op
+ \op v0.2d, v1.2d, #0.0
+ \op v0.2s, v1.2s, #0.0
+ \op v0.4s, v1.4s, #0.0
+ \op v0.4h, v1.4h, #0.0
+ \op v0.8h, v1.8h, #0.0
+ .endm
+
+ tworeg_zero fcmgt
+ tworeg_zero fcmge
+ tworeg_zero fcmeq
+ tworeg_zero fcmle
+ tworeg_zero fcmlt
+
+ .macro tworeg_misc, op
+ \op v0.2d, v1.2d
+ \op v0.2s, v1.2s
+ \op v0.4s, v1.4s
+ \op v0.4h, v1.4h
+ \op v0.8h, v1.8h
+ .endm
+
+ tworeg_misc fabs
+ tworeg_misc fneg
+
+ tworeg_misc frintn
+ tworeg_misc frinta
+ tworeg_misc frintp
+
+ tworeg_misc frintm
+ tworeg_misc frintx
+ tworeg_misc frintz
+ tworeg_misc frinti
+
+ tworeg_misc fcvtns
+ tworeg_misc fcvtnu
+ tworeg_misc fcvtps
+ tworeg_misc fcvtpu
+
+ tworeg_misc fcvtms
+ tworeg_misc fcvtmu
+ tworeg_misc fcvtzs
+ tworeg_misc fcvtzu
+
+ tworeg_misc fcvtas
+ tworeg_misc fcvtau
+
+ tworeg_misc scvtf
+ tworeg_misc ucvtf
+ tworeg_misc frecpe
+ tworeg_misc frsqrte
+ tworeg_misc fsqrt
diff --git a/gas/testsuite/gas/aarch64/verbose-error.l b/gas/testsuite/gas/aarch64/verbose-error.l
index 3d2c99e..314a5cc 100644
--- a/gas/testsuite/gas/aarch64/verbose-error.l
+++ b/gas/testsuite/gas/aarch64/verbose-error.l
@@ -67,10 +67,9 @@
[^:]*:22: Info: rev32 v4.8h,v5.8h
[^:]*:24: Error: operand mismatch -- `frintn v6.8b,v7.8b'
[^:]*:24: Info: did you mean this\?
-[^:]*:24: Info: frintn v6.2s,v7.2s
+[^:]*:24: Info: frintn v6.4h,v7.4h
[^:]*:24: Info: other valid variant\(s\):
-[^:]*:24: Info: frintn v6.4s,v7.4s
-[^:]*:24: Info: frintn v6.2d,v7.2d
+[^:]*:24: Info: frintn v6.8h,v7.8h
[^:]*:26: Error: operand mismatch -- `rev64 v8.2d,v9.2d'
[^:]*:26: Info: did you mean this\?
[^:]*:26: Info: rev64 v8.8b,v9.8b
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index ba855ed..3e99ec6 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -752,6 +752,13 @@
QLF2(V_4S , V_4S ), \
}
+/* e.g. FCMGT <Vd>.<T>, <Vd>.<T>>, #0.0. */
+#define QL_V2SAMEH \
+{ \
+ QLF2 (V_4H, V_4H), \
+ QLF2 (V_8H, V_8H), \
+}
+
/* e.g. REV16 <Vd>.<T>, <Vn>.<T>. */
#define QL_V2SAMEB \
{ \
@@ -1503,21 +1510,51 @@ struct aarch64_opcode aarch64_opcode_table[] =
{"fcvtl", 0xe217800, 0xffbffc00, asimdmisc, OP_FCVTL, SIMD, OP2 (Vd, Vn), QL_V2LONGHS, F_MISC},
{"fcvtl2", 0x4e217800, 0xffbffc00, asimdmisc, OP_FCVTL2, SIMD, OP2 (Vd, Vn), QL_V2LONGHS2, F_MISC},
{"frintn", 0xe218800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
+ {"frintn", 0xe798800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
+ OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
{"frintm", 0xe219800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
+ {"frintm", 0xe799800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
+ OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
{"fcvtns", 0xe21a800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
+ {"fcvtns", 0xe79a800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
+ OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
{"fcvtms", 0xe21b800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
+ {"fcvtms", 0xe79b800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
+ OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
{"fcvtas", 0xe21c800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
+ {"fcvtas", 0xe79c800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
+ OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
{"scvtf", 0xe21d800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
+ {"scvtf", 0xe79d800, 0xbfbffc00, asimdmisc, 0, SIMD_F16,
+ OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
{"fcmgt", 0xea0c800, 0xbfbffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, FPIMM0), QL_V2SAMESD, F_SIZEQ},
+ {"fcmgt", 0xef8c800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
+ OP3 (Vd, Vn, FPIMM0), QL_V2SAMEH, F_SIZEQ},
{"fcmeq", 0xea0d800, 0xbfbffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, FPIMM0), QL_V2SAMESD, F_SIZEQ},
+ {"fcmeq", 0xef8d800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
+ OP3 (Vd, Vn, FPIMM0), QL_V2SAMEH, F_SIZEQ},
{"fcmlt", 0xea0e800, 0xbfbffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, FPIMM0), QL_V2SAMESD, F_SIZEQ},
+ {"fcmlt", 0xef8e800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
+ OP3 (Vd, Vn, FPIMM0), QL_V2SAMEH, F_SIZEQ},
{"fabs", 0xea0f800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
+ {"fabs", 0xef8f800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
+ OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
{"frintp", 0xea18800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
+ {"frintp", 0xef98800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
+ OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
{"frintz", 0xea19800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
+ {"frintz", 0xef99800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
+ OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
{"fcvtps", 0xea1a800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
+ {"fcvtps", 0xef9a800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
+ OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
{"fcvtzs", 0xea1b800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
+ {"fcvtzs", 0xef9b800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
+ OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
{"urecpe", 0xea1c800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMES, F_SIZEQ},
{"frecpe", 0xea1d800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
+ {"frecpe", 0xef9d800, 0xbfbffc00, asimdmisc, 0, SIMD_F16,
+ OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
{"rev32", 0x2e200800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMEBH, F_SIZEQ},
{"uaddlp", 0x2e202800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2PAIRWISELONGBHS, F_SIZEQ},
{"usqadd", 0x2e203800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAME, F_SIZEQ},
@@ -1536,23 +1573,51 @@ struct aarch64_opcode aarch64_opcode_table[] =
{"fcvtxn", 0x2e616800, 0xfffffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2NARRS, 0},
{"fcvtxn2", 0x6e616800, 0xfffffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2NARRS2, 0},
{"frinta", 0x2e218800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
+ {"frinta", 0x2e798800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
+ OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
{"frintx", 0x2e219800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
+ {"frintx", 0x2e799800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
+ OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
{"fcvtnu", 0x2e21a800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
+ {"fcvtnu", 0x2e79a800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
+ OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
{"fcvtmu", 0x2e21b800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
+ {"fcvtmu", 0x2e79b800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
+ OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
{"fcvtau", 0x2e21c800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
+ {"fcvtau", 0x2e79c800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
+ OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
{"ucvtf", 0x2e21d800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
+ {"ucvtf", 0x2e79d800, 0xbfbffc00, asimdmisc, 0, SIMD_F16,
+ OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
{"not", 0x2e205800, 0xbffffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMEB, F_SIZEQ | F_HAS_ALIAS},
{"mvn", 0x2e205800, 0xbffffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMEB, F_SIZEQ | F_ALIAS},
{"rbit", 0x2e605800, 0xbffffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMEB, F_SIZEQ},
{"fcmge", 0x2ea0c800, 0xbfbffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, FPIMM0), QL_V2SAMESD, F_SIZEQ},
+ {"fcmge", 0x2ef8c800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
+ OP3 (Vd, Vn, FPIMM0), QL_V2SAMEH, F_SIZEQ},
{"fcmle", 0x2ea0d800, 0xbfbffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, FPIMM0), QL_V2SAMESD, F_SIZEQ},
+ {"fcmle", 0x2ef8d800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
+ OP3 (Vd, Vn, FPIMM0), QL_V2SAMEH, F_SIZEQ},
{"fneg", 0x2ea0f800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
+ {"fneg", 0x2ef8f800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
+ OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
{"frinti", 0x2ea19800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
+ {"frinti", 0x2ef99800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
+ OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
{"fcvtpu", 0x2ea1a800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
+ {"fcvtpu", 0x2ef9a800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
+ OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
{"fcvtzu", 0x2ea1b800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
+ {"fcvtzu", 0x2ef9b800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
+ OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
{"ursqrte", 0x2ea1c800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMES, F_SIZEQ},
{"frsqrte", 0x2ea1d800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
+ {"frsqrte", 0x2ef9d800, 0xbfbffc00, asimdmisc, 0, SIMD_F16,
+ OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
{"fsqrt", 0x2ea1f800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
+ {"fsqrt", 0x2ef9f800, 0xbfbffc00, asimdmisc, 0, SIMD_F16,
+ OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
/* AdvSIMD ZIP/UZP/TRN. */
{"uzp1", 0xe001800, 0xbf20fc00, asimdperm, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
{"trn1", 0xe002800, 0xbf20fc00, asimdperm, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
--
2.1.4