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[AArch64][PATCH 2/14] Support ARMv8.2 FP16 Vector Three Same instructions.


ARMv8.2 adds 16-bit floating point operations as an optional extension
to floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Three Register Same, making them
available when +simd+fp16 is enabled.

The instructions added are: FMAXNM, FMAXNMP, FNMINNM, FMINNMP, FMLA,
FMLS, FADD, FADDP, FSUB, FABD, FMULX, FMUL, FCMEQ, FCMGE, FCMGT, FACGE,
FACGT, FMAX, FMAXP, FMIN, FMINP, FRECPS, FDIV and FRSQRTS.

The general form for these instructions is
  <OP> <Vd>.<T>, <Vs>.<T>, <Vm>.<T>
  where T is 4h or 8h.

Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.

Ok for trunk?
Matthew

gas/testsuite/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

	* gas/aarch64/advsimd-fp16.d: New.
	* gas/aarch64/advsimd-fp16.s: New.

opcodes/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-opc-2.c: Regenerate.
	* aarch64-tbl.h (QL_V3SAMEH): New.
	(aarch64_opcode_table): Add fp16 versions of fmaxnm, fmla, fadd,
	fmulx, fcmeq, fmax, frecps, fminnm, fmls, fsub, fmin, frsqrts,
	fmaxnmp, faddp, fmul, fcmge, facge, fmaxp, fdiv, fminnmp, fabd,
	fcmgt, facgt and fminp to the vector three same group.

>From 4d2bcd47b917d697536c59c85529802cc6ba207c Mon Sep 17 00:00:00 2001
From: Matthew Wahab <matthew.wahab@arm.com>
Date: Tue, 8 Sep 2015 18:45:10 +0100
Subject: [PATCH 02/14] [AArch64] Add FP16 Vector three-same instructions (I).

---
 gas/testsuite/gas/aarch64/advsimd-fp16.d |  169 +++
 gas/testsuite/gas/aarch64/advsimd-fp16.s |   40 +
 opcodes/aarch64-asm-2.c                  |  652 ++++-----
 opcodes/aarch64-dis-2.c                  | 2216 +++++++++++++++++-------------
 opcodes/aarch64-opc-2.c                  |  114 +-
 opcodes/aarch64-tbl.h                    |   55 +
 6 files changed, 1887 insertions(+), 1359 deletions(-)
 create mode 100644 gas/testsuite/gas/aarch64/advsimd-fp16.d
 create mode 100644 gas/testsuite/gas/aarch64/advsimd-fp16.s

diff --git a/gas/testsuite/gas/aarch64/advsimd-fp16.d b/gas/testsuite/gas/aarch64/advsimd-fp16.d
new file mode 100644
index 0000000..5b5e694
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/advsimd-fp16.d
@@ -0,0 +1,169 @@
+#as: -march=armv8.2-a+simd+fp16
+#objdump: -dr
+
+.*:     file format .*
+
+Disassembly of section \.text:
+
+0000000000000000 <.*>:
+   [0-9a-f]+:	4e63c441 	fmaxnm	v1.2d, v2.2d, v3.2d
+   [0-9a-f]+:	0e23c441 	fmaxnm	v1.2s, v2.2s, v3.2s
+   [0-9a-f]+:	4e23c441 	fmaxnm	v1.4s, v2.4s, v3.4s
+   [0-9a-f]+:	0e400400 	fmaxnm	v0.4h, v0.4h, v0.4h
+  [0-9a-f]+:	0e430441 	fmaxnm	v1.4h, v2.4h, v3.4h
+  [0-9a-f]+:	4e400400 	fmaxnm	v0.8h, v0.8h, v0.8h
+  [0-9a-f]+:	4e430441 	fmaxnm	v1.8h, v2.8h, v3.8h
+  [0-9a-f]+:	6e63c441 	fmaxnmp	v1.2d, v2.2d, v3.2d
+  [0-9a-f]+:	2e23c441 	fmaxnmp	v1.2s, v2.2s, v3.2s
+  [0-9a-f]+:	6e23c441 	fmaxnmp	v1.4s, v2.4s, v3.4s
+  [0-9a-f]+:	2e400400 	fmaxnmp	v0.4h, v0.4h, v0.4h
+  [0-9a-f]+:	2e430441 	fmaxnmp	v1.4h, v2.4h, v3.4h
+  [0-9a-f]+:	6e400400 	fmaxnmp	v0.8h, v0.8h, v0.8h
+  [0-9a-f]+:	6e430441 	fmaxnmp	v1.8h, v2.8h, v3.8h
+  [0-9a-f]+:	4ee3c441 	fminnm	v1.2d, v2.2d, v3.2d
+  [0-9a-f]+:	0ea3c441 	fminnm	v1.2s, v2.2s, v3.2s
+  [0-9a-f]+:	4ea3c441 	fminnm	v1.4s, v2.4s, v3.4s
+  [0-9a-f]+:	0ec00400 	fminnm	v0.4h, v0.4h, v0.4h
+  [0-9a-f]+:	0ec30441 	fminnm	v1.4h, v2.4h, v3.4h
+  [0-9a-f]+:	4ec00400 	fminnm	v0.8h, v0.8h, v0.8h
+  [0-9a-f]+:	4ec30441 	fminnm	v1.8h, v2.8h, v3.8h
+  [0-9a-f]+:	6ee3c441 	fminnmp	v1.2d, v2.2d, v3.2d
+  [0-9a-f]+:	2ea3c441 	fminnmp	v1.2s, v2.2s, v3.2s
+  [0-9a-f]+:	6ea3c441 	fminnmp	v1.4s, v2.4s, v3.4s
+  [0-9a-f]+:	2ec00400 	fminnmp	v0.4h, v0.4h, v0.4h
+  [0-9a-f]+:	2ec30441 	fminnmp	v1.4h, v2.4h, v3.4h
+  [0-9a-f]+:	6ec00400 	fminnmp	v0.8h, v0.8h, v0.8h
+  [0-9a-f]+:	6ec30441 	fminnmp	v1.8h, v2.8h, v3.8h
+  [0-9a-f]+:	4e63cc41 	fmla	v1.2d, v2.2d, v3.2d
+  [0-9a-f]+:	0e23cc41 	fmla	v1.2s, v2.2s, v3.2s
+  [0-9a-f]+:	4e23cc41 	fmla	v1.4s, v2.4s, v3.4s
+  [0-9a-f]+:	0e400c00 	fmla	v0.4h, v0.4h, v0.4h
+  [0-9a-f]+:	0e430c41 	fmla	v1.4h, v2.4h, v3.4h
+  [0-9a-f]+:	4e400c00 	fmla	v0.8h, v0.8h, v0.8h
+  [0-9a-f]+:	4e430c41 	fmla	v1.8h, v2.8h, v3.8h
+  [0-9a-f]+:	4ee3cc41 	fmls	v1.2d, v2.2d, v3.2d
+  [0-9a-f]+:	0ea3cc41 	fmls	v1.2s, v2.2s, v3.2s
+  [0-9a-f]+:	4ea3cc41 	fmls	v1.4s, v2.4s, v3.4s
+  [0-9a-f]+:	0ec00c00 	fmls	v0.4h, v0.4h, v0.4h
+  [0-9a-f]+:	0ec30c41 	fmls	v1.4h, v2.4h, v3.4h
+  [0-9a-f]+:	4ec00c00 	fmls	v0.8h, v0.8h, v0.8h
+  [0-9a-f]+:	4ec30c41 	fmls	v1.8h, v2.8h, v3.8h
+  [0-9a-f]+:	4e63d441 	fadd	v1.2d, v2.2d, v3.2d
+  [0-9a-f]+:	0e23d441 	fadd	v1.2s, v2.2s, v3.2s
+  [0-9a-f]+:	4e23d441 	fadd	v1.4s, v2.4s, v3.4s
+  [0-9a-f]+:	0e401400 	fadd	v0.4h, v0.4h, v0.4h
+  [0-9a-f]+:	0e431441 	fadd	v1.4h, v2.4h, v3.4h
+  [0-9a-f]+:	4e401400 	fadd	v0.8h, v0.8h, v0.8h
+  [0-9a-f]+:	4e431441 	fadd	v1.8h, v2.8h, v3.8h
+  [0-9a-f]+:	6e63d441 	faddp	v1.2d, v2.2d, v3.2d
+  [0-9a-f]+:	2e23d441 	faddp	v1.2s, v2.2s, v3.2s
+  [0-9a-f]+:	6e23d441 	faddp	v1.4s, v2.4s, v3.4s
+  [0-9a-f]+:	2e401400 	faddp	v0.4h, v0.4h, v0.4h
+  [0-9a-f]+:	2e431441 	faddp	v1.4h, v2.4h, v3.4h
+  [0-9a-f]+:	6e401400 	faddp	v0.8h, v0.8h, v0.8h
+  [0-9a-f]+:	6e431441 	faddp	v1.8h, v2.8h, v3.8h
+  [0-9a-f]+:	4ee3d441 	fsub	v1.2d, v2.2d, v3.2d
+  [0-9a-f]+:	0ea3d441 	fsub	v1.2s, v2.2s, v3.2s
+  [0-9a-f]+:	4ea3d441 	fsub	v1.4s, v2.4s, v3.4s
+  [0-9a-f]+:	0ec01400 	fsub	v0.4h, v0.4h, v0.4h
+  [0-9a-f]+:	0ec31441 	fsub	v1.4h, v2.4h, v3.4h
+  [0-9a-f]+:	4ec01400 	fsub	v0.8h, v0.8h, v0.8h
+  [0-9a-f]+:	4ec31441 	fsub	v1.8h, v2.8h, v3.8h
+  [0-9a-f]+:	4e63dc41 	fmulx	v1.2d, v2.2d, v3.2d
+ [0-9a-f]+:	0e23dc41 	fmulx	v1.2s, v2.2s, v3.2s
+ [0-9a-f]+:	4e23dc41 	fmulx	v1.4s, v2.4s, v3.4s
+ [0-9a-f]+:	0e401c00 	fmulx	v0.4h, v0.4h, v0.4h
+ [0-9a-f]+:	0e431c41 	fmulx	v1.4h, v2.4h, v3.4h
+ [0-9a-f]+:	4e401c00 	fmulx	v0.8h, v0.8h, v0.8h
+ [0-9a-f]+:	4e431c41 	fmulx	v1.8h, v2.8h, v3.8h
+ [0-9a-f]+:	6e63dc41 	fmul	v1.2d, v2.2d, v3.2d
+ [0-9a-f]+:	2e23dc41 	fmul	v1.2s, v2.2s, v3.2s
+ [0-9a-f]+:	6e23dc41 	fmul	v1.4s, v2.4s, v3.4s
+ [0-9a-f]+:	2e401c00 	fmul	v0.4h, v0.4h, v0.4h
+ [0-9a-f]+:	2e431c41 	fmul	v1.4h, v2.4h, v3.4h
+ [0-9a-f]+:	6e401c00 	fmul	v0.8h, v0.8h, v0.8h
+ [0-9a-f]+:	6e431c41 	fmul	v1.8h, v2.8h, v3.8h
+ [0-9a-f]+:	4e63e441 	fcmeq	v1.2d, v2.2d, v3.2d
+ [0-9a-f]+:	0e23e441 	fcmeq	v1.2s, v2.2s, v3.2s
+ [0-9a-f]+:	4e23e441 	fcmeq	v1.4s, v2.4s, v3.4s
+ [0-9a-f]+:	0e402400 	fcmeq	v0.4h, v0.4h, v0.4h
+ [0-9a-f]+:	0e432441 	fcmeq	v1.4h, v2.4h, v3.4h
+ [0-9a-f]+:	4e402400 	fcmeq	v0.8h, v0.8h, v0.8h
+ [0-9a-f]+:	4e432441 	fcmeq	v1.8h, v2.8h, v3.8h
+ [0-9a-f]+:	6e63e441 	fcmge	v1.2d, v2.2d, v3.2d
+ [0-9a-f]+:	2e23e441 	fcmge	v1.2s, v2.2s, v3.2s
+ [0-9a-f]+:	6e23e441 	fcmge	v1.4s, v2.4s, v3.4s
+ [0-9a-f]+:	2e402400 	fcmge	v0.4h, v0.4h, v0.4h
+ [0-9a-f]+:	2e432441 	fcmge	v1.4h, v2.4h, v3.4h
+ [0-9a-f]+:	6e402400 	fcmge	v0.8h, v0.8h, v0.8h
+ [0-9a-f]+:	6e432441 	fcmge	v1.8h, v2.8h, v3.8h
+ [0-9a-f]+:	6ee3e441 	fcmgt	v1.2d, v2.2d, v3.2d
+ [0-9a-f]+:	2ea3e441 	fcmgt	v1.2s, v2.2s, v3.2s
+ [0-9a-f]+:	6ea3e441 	fcmgt	v1.4s, v2.4s, v3.4s
+ [0-9a-f]+:	2ec02400 	fcmgt	v0.4h, v0.4h, v0.4h
+ [0-9a-f]+:	2ec32441 	fcmgt	v1.4h, v2.4h, v3.4h
+ [0-9a-f]+:	6ec02400 	fcmgt	v0.8h, v0.8h, v0.8h
+ [0-9a-f]+:	6ec32441 	fcmgt	v1.8h, v2.8h, v3.8h
+ [0-9a-f]+:	6e63ec41 	facge	v1.2d, v2.2d, v3.2d
+ [0-9a-f]+:	2e23ec41 	facge	v1.2s, v2.2s, v3.2s
+ [0-9a-f]+:	6e23ec41 	facge	v1.4s, v2.4s, v3.4s
+ [0-9a-f]+:	2e402c00 	facge	v0.4h, v0.4h, v0.4h
+ [0-9a-f]+:	2e432c41 	facge	v1.4h, v2.4h, v3.4h
+ [0-9a-f]+:	6e402c00 	facge	v0.8h, v0.8h, v0.8h
+ [0-9a-f]+:	6e432c41 	facge	v1.8h, v2.8h, v3.8h
+ [0-9a-f]+:	6ee3ec41 	facgt	v1.2d, v2.2d, v3.2d
+ [0-9a-f]+:	2ea3ec41 	facgt	v1.2s, v2.2s, v3.2s
+ [0-9a-f]+:	6ea3ec41 	facgt	v1.4s, v2.4s, v3.4s
+ [0-9a-f]+:	2ec02c00 	facgt	v0.4h, v0.4h, v0.4h
+ [0-9a-f]+:	2ec32c41 	facgt	v1.4h, v2.4h, v3.4h
+ [0-9a-f]+:	6ec02c00 	facgt	v0.8h, v0.8h, v0.8h
+ [0-9a-f]+:	6ec32c41 	facgt	v1.8h, v2.8h, v3.8h
+ [0-9a-f]+:	4e63f441 	fmax	v1.2d, v2.2d, v3.2d
+ [0-9a-f]+:	0e23f441 	fmax	v1.2s, v2.2s, v3.2s
+ [0-9a-f]+:	4e23f441 	fmax	v1.4s, v2.4s, v3.4s
+ [0-9a-f]+:	0e403400 	fmax	v0.4h, v0.4h, v0.4h
+ [0-9a-f]+:	0e433441 	fmax	v1.4h, v2.4h, v3.4h
+ [0-9a-f]+:	4e403400 	fmax	v0.8h, v0.8h, v0.8h
+ [0-9a-f]+:	4e433441 	fmax	v1.8h, v2.8h, v3.8h
+ [0-9a-f]+:	6e63f441 	fmaxp	v1.2d, v2.2d, v3.2d
+ [0-9a-f]+:	2e23f441 	fmaxp	v1.2s, v2.2s, v3.2s
+ [0-9a-f]+:	6e23f441 	fmaxp	v1.4s, v2.4s, v3.4s
+ [0-9a-f]+:	2e403400 	fmaxp	v0.4h, v0.4h, v0.4h
+ [0-9a-f]+:	2e433441 	fmaxp	v1.4h, v2.4h, v3.4h
+ [0-9a-f]+:	6e403400 	fmaxp	v0.8h, v0.8h, v0.8h
+ [0-9a-f]+:	6e433441 	fmaxp	v1.8h, v2.8h, v3.8h
+ [0-9a-f]+:	4ee3f441 	fmin	v1.2d, v2.2d, v3.2d
+ [0-9a-f]+:	0ea3f441 	fmin	v1.2s, v2.2s, v3.2s
+ [0-9a-f]+:	4ea3f441 	fmin	v1.4s, v2.4s, v3.4s
+ [0-9a-f]+:	0ec03400 	fmin	v0.4h, v0.4h, v0.4h
+ [0-9a-f]+:	0ec33441 	fmin	v1.4h, v2.4h, v3.4h
+ [0-9a-f]+:	4ec03400 	fmin	v0.8h, v0.8h, v0.8h
+ [0-9a-f]+:	4ec33441 	fmin	v1.8h, v2.8h, v3.8h
+ [0-9a-f]+:	6ee3f441 	fminp	v1.2d, v2.2d, v3.2d
+ [0-9a-f]+:	2ea3f441 	fminp	v1.2s, v2.2s, v3.2s
+ [0-9a-f]+:	6ea3f441 	fminp	v1.4s, v2.4s, v3.4s
+ [0-9a-f]+:	2ec03400 	fminp	v0.4h, v0.4h, v0.4h
+ [0-9a-f]+:	2ec33441 	fminp	v1.4h, v2.4h, v3.4h
+ [0-9a-f]+:	6ec03400 	fminp	v0.8h, v0.8h, v0.8h
+ [0-9a-f]+:	6ec33441 	fminp	v1.8h, v2.8h, v3.8h
+ [0-9a-f]+:	4e63fc41 	frecps	v1.2d, v2.2d, v3.2d
+ [0-9a-f]+:	0e23fc41 	frecps	v1.2s, v2.2s, v3.2s
+ [0-9a-f]+:	4e23fc41 	frecps	v1.4s, v2.4s, v3.4s
+ [0-9a-f]+:	0e403c00 	frecps	v0.4h, v0.4h, v0.4h
+ [0-9a-f]+:	0e433c41 	frecps	v1.4h, v2.4h, v3.4h
+ [0-9a-f]+:	4e403c00 	frecps	v0.8h, v0.8h, v0.8h
+ [0-9a-f]+:	4e433c41 	frecps	v1.8h, v2.8h, v3.8h
+ [0-9a-f]+:	6e63fc41 	fdiv	v1.2d, v2.2d, v3.2d
+ [0-9a-f]+:	2e23fc41 	fdiv	v1.2s, v2.2s, v3.2s
+ [0-9a-f]+:	6e23fc41 	fdiv	v1.4s, v2.4s, v3.4s
+ [0-9a-f]+:	2e403c00 	fdiv	v0.4h, v0.4h, v0.4h
+ [0-9a-f]+:	2e433c41 	fdiv	v1.4h, v2.4h, v3.4h
+ [0-9a-f]+:	6e403c00 	fdiv	v0.8h, v0.8h, v0.8h
+ [0-9a-f]+:	6e433c41 	fdiv	v1.8h, v2.8h, v3.8h
+ [0-9a-f]+:	4ee3fc41 	frsqrts	v1.2d, v2.2d, v3.2d
+ [0-9a-f]+:	0ea3fc41 	frsqrts	v1.2s, v2.2s, v3.2s
+ [0-9a-f]+:	4ea3fc41 	frsqrts	v1.4s, v2.4s, v3.4s
+ [0-9a-f]+:	0ec03c00 	frsqrts	v0.4h, v0.4h, v0.4h
+ [0-9a-f]+:	0ec33c41 	frsqrts	v1.4h, v2.4h, v3.4h
+ [0-9a-f]+:	4ec03c00 	frsqrts	v0.8h, v0.8h, v0.8h
+ [0-9a-f]+:	4ec33c41 	frsqrts	v1.8h, v2.8h, v3.8h
diff --git a/gas/testsuite/gas/aarch64/advsimd-fp16.s b/gas/testsuite/gas/aarch64/advsimd-fp16.s
new file mode 100644
index 0000000..3649ca2
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/advsimd-fp16.s
@@ -0,0 +1,40 @@
+/* simdhp.s Test file for AArch64 half-precision floating-point
+   vector instructions.  */
+
+	/* Vector three-same.  */
+
+	.macro three_same, op
+	\op	v1.2d, v2.2d, v3.2d
+	\op	v1.2s, v2.2s, v3.2s
+	\op	v1.4s, v2.4s, v3.4s
+	\op	v0.4h, v0.4h, v0.4h
+	\op	v1.4h, v2.4h, v3.4h
+	\op	v0.8h, v0.8h, v0.8h
+	\op	v1.8h, v2.8h, v3.8h
+	.endm
+
+	.text
+
+	three_same fmaxnm
+	three_same fmaxnmp
+	three_same fminnm
+	three_same fminnmp
+	three_same fmla
+	three_same fmls
+	three_same fadd
+	three_same faddp
+	three_same fsub
+	three_same fmulx
+	three_same fmul
+	three_same fcmeq
+	three_same fcmge
+	three_same fcmgt
+	three_same facge
+	three_same facgt
+	three_same fmax
+	three_same fmaxp
+	three_same fmin
+	three_same fminp
+	three_same frecps
+	three_same fdiv
+	three_same frsqrts
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index bd6b265..f2c7c7f 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -921,6 +921,13 @@
   QLF3(V_2D , V_2D , V_2D )	\
 }
 
+/* e.g. FMAXNM <Vd>.<T>, <Vn>.<T>, <Vm>.<T>.  */
+#define QL_V3SAMEH		\
+{				\
+  QLF3 (V_4H , V_4H , V_4H ),	\
+  QLF3 (V_8H , V_8H , V_8H ),	\
+}
+
 /* e.g. SQDMLAL<Q> <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>.  */
 #define QL_V3LONGHS		\
 {				\
@@ -1578,19 +1585,43 @@ struct aarch64_opcode aarch64_opcode_table[] =
   {"sqdmulh", 0xe20b400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEHS, F_SIZEQ},
   {"addp", 0xe20bc00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
   {"fmaxnm", 0xe20c400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
+  {"fmaxnm", 0xe400400, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
+   OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
   {"fmla", 0xe20cc00, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
+  {"fmla", 0xe400c00, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
+   OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
   {"fadd", 0xe20d400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
+  {"fadd", 0xe401400, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
+   OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
   {"fmulx", 0xe20dc00, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
+  {"fmulx", 0xe401c00, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
+   OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
   {"fcmeq", 0xe20e400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
+  {"fcmeq", 0xe402400, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
+   OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
   {"fmax", 0xe20f400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
+  {"fmax", 0xe403400, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
+   OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
   {"frecps", 0xe20fc00, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
+  {"frecps", 0xe403c00, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
+   OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
   {"and", 0xe201c00, 0xbfe0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ},
   {"bic", 0xe601c00, 0xbfe0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ},
   {"fminnm", 0xea0c400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
+  {"fminnm", 0xec00400, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
+   OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
   {"fmls", 0xea0cc00, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
+  {"fmls", 0xec00c00, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
+   OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
   {"fsub", 0xea0d400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
+  {"fsub", 0xec01400, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
+   OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
   {"fmin", 0xea0f400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
+  {"fmin", 0xec03400, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
+   OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
   {"frsqrts", 0xea0fc00, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
+  {"frsqrts", 0xec03c00, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
+   OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
   {"orr", 0xea01c00, 0xbfe0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_HAS_ALIAS | F_SIZEQ},
   {"mov", 0xea01c00, 0xbfe0fc00, asimdsame, OP_MOV_V, SIMD, OP2 (Vd, Vn), QL_V2SAMEB, F_ALIAS | F_CONV},
   {"orn", 0xee01c00, 0xbfe0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ},
@@ -1617,19 +1648,43 @@ struct aarch64_opcode aarch64_opcode_table[] =
   {"uminp", 0x2e20ac00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
   {"sqrdmulh", 0x2e20b400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEHS, F_SIZEQ},
   {"fmaxnmp", 0x2e20c400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
+  {"fmaxnmp", 0x2e400400, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
+   OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
   {"faddp", 0x2e20d400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
+  {"faddp", 0x2e401400, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
+   OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
   {"fmul", 0x2e20dc00, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
+  {"fmul", 0x2e401c00, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
+   OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
   {"fcmge", 0x2e20e400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
+  {"fcmge", 0x2e402400, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
+   OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
   {"facge", 0x2e20ec00, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
+  {"facge", 0x2e402c00, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
+   OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
   {"fmaxp", 0x2e20f400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
+  {"fmaxp", 0x2e403400, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
+   OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
   {"fdiv", 0x2e20fc00, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
+  {"fdiv", 0x2e403c00, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
+   OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
   {"eor", 0x2e201c00, 0xbfe0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ},
   {"bsl", 0x2e601c00, 0xbfe0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ},
   {"fminnmp", 0x2ea0c400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
+  {"fminnmp", 0x2ec00400, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
+   OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
   {"fabd", 0x2ea0d400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
+  {"fabd", 0x2ec01400, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
+   OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
   {"fcmgt", 0x2ea0e400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
+  {"fcmgt", 0x2ec02400, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
+   OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
   {"facgt", 0x2ea0ec00, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
+  {"facgt", 0x2ec02c00, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
+   OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
   {"fminp", 0x2ea0f400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
+  {"fminp", 0x2ec03400, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
+   OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
   {"bit", 0x2ea01c00, 0xbfe0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ},
   {"bif", 0x2ee01c00, 0xbfe0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ},
   /* AdvSIMD three same extension.  */
-- 
2.1.4


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