This is the mail archive of the
binutils@sourceware.org
mailing list for the binutils project.
[PATCH 1/2][ARM][binutils] Add support for ARMv8.1 Adv.SIMD extension.
- From: Matthew Wahab <matthew dot wahab at arm dot com>
- To: "binutils at sourceware dot org" <binutils at sourceware dot org>
- Date: Thu, 21 May 2015 10:48:31 +0100
- Subject: [PATCH 1/2][ARM][binutils] Add support for ARMv8.1 Adv.SIMD extension.
- Authentication-results: sourceware.org; auth=none
The ARMv8.1 architecture introduces two instructions, "vqrdmlah" and "vqrdmlsh",
and their variants to the ARM Advanced SIMD instruction set. This patch adds
support for these instructions to binutils. A following patch will add support
to gas.
Tested for arm-none-linux-gnueabihf with check-binutils and check-gas.
Ok for trunk?
Matthew
include/opcode/
2015-05-21 Matthew Wahab <matthew.wahab@arm.com>
* arm.h (FPU_NEON_EXT_RDMA): New.
(FPU_ARCH_NEON_VFP_ARMV8_1): New.
opcodes/
2015-05-21 Matthew Wahab <matthew.wahab@arm.com>
* arm-dis.c (neon_opcodes): Add "vqrdmlah" and "vqrdmlsh".
From 6429eb1da008688fef5f50b33fbb34b2efa52052 Mon Sep 17 00:00:00 2001
From: Matthew Wahab <matthew.wahab@arm.com>
Date: Thu, 14 May 2015 09:38:01 +0100
Subject: [PATCH 1/2] [ARM][binutils] Support v8.1 Adv.SIMD extension
Change-Id: I91cdeb4dc7a4a1e5a3c48a9e053ade2ff9c4d5ed
---
include/opcode/arm.h | 6 ++++++
opcodes/arm-dis.c | 19 +++++++++++++++++++
2 files changed, 25 insertions(+)
diff --git a/include/opcode/arm.h b/include/opcode/arm.h
index 1bf6b3c..a8bcced 100644
--- a/include/opcode/arm.h
+++ b/include/opcode/arm.h
@@ -83,6 +83,7 @@
#define FPU_CRYPTO_EXT_ARMV8 0x00008000 /* Crypto for ARMv8. */
#define CRC_EXT_ARMV8 0x00004000 /* CRC32 for ARMv8. */
#define FPU_VFP_EXT_ARMV8xD 0x00002000 /* Single-precision FP for ARMv8. */
+#define FPU_NEON_EXT_RDMA 0x00001000 /* v8.1 Adv.SIMD extensions. */
/* Architectures are the sum of the base and extensions. The ARM ARM (rev E)
defines the following: ARMv3, ARMv3M, ARMv4xM, ARMv4, ARMv4TxM, ARMv4T,
@@ -201,6 +202,11 @@
#define FPU_ARCH_CRYPTO_NEON_VFP_ARMV8 \
ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8 | FPU_NEON_ARMV8 | FPU_VFP_ARMV8)
#define ARCH_CRC_ARMV8 ARM_FEATURE_COPROC (CRC_EXT_ARMV8)
+#define FPU_ARCH_NEON_VFP_ARMV8_1 \
+ ARM_FEATURE_COPROC (FPU_NEON_ARMV8 \
+ | FPU_VFP_ARMV8 \
+ | FPU_NEON_EXT_RDMA)
+
#define FPU_ARCH_ENDIAN_PURE ARM_FEATURE_COPROC (FPU_ENDIAN_PURE)
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index 1585a4f..1725385 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -1194,6 +1194,12 @@ static const struct opcode32 neon_opcodes[] =
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2000a10, 0xfe800f10,
"vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
+ {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
+ 0xf3000b10, 0xff800f10,
+ "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
+ {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
+ 0xf3000c10, 0xff800f10,
+ "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
/* One register and an immediate value. */
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
@@ -1447,6 +1453,19 @@ static const struct opcode32 neon_opcodes[] =
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2800a40, 0xfe800f50,
"vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
+ {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
+ 0xf2800e40, 0xff800f50,
+ "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
+ {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
+ 0xf2800f40, 0xff800f50,
+ "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
+ {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
+ 0xf3800e40, 0xff800f50,
+ "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
+ {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
+ 0xf3800f40, 0xff800f50,
+ "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
+ },
/* Element and structure load/store. */
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
--
1.9.1