This is the mail archive of the
binutils@sourceware.org
mailing list for the binutils project.
[PATCH][ARM][1/2] Cleanup mixed use of "cpu_variant" and selected_cpu"
- From: Jiong Wang <jiong dot wang at arm dot com>
- To: "binutils at sourceware dot org" <binutils at sourceware dot org>
- Date: Thu, 14 Aug 2014 10:03:04 +0100
- Subject: [PATCH][ARM][1/2] Cleanup mixed use of "cpu_variant" and selected_cpu"
- Authentication-results: sourceware.org; auth=none
currently, gas for arm32 have several variables to track cpu features:
cpu_variant
selected_cpu
arm_arch_used
thumb_arch_used
and there are some wrong usage of cpu_variant and selected_cpu which actually affect
binary correctness.
I checked the log, there was cpu_variant only, but later a new variable "selected_cpu"
was introduced for TAG_cpu attribute generation only, since then people start to
use them in a mixed way.
for selected_cpu, its value depends on arch/cpu options or directives, if none of
them found, then its default value is zero.
while for cpu_variant, its default value is a mask contains all features, and will be
updated to the value of selected_cpu *if the value of selected_cpu is not zero*.
so if no arch/cpu options/directives specified, then cpu_variant *accept* everything
while *selected_cpu* reject everything.
then if the code in parsing stage use cpu_variant, it will accept some features, but
reject them in later fixup stage silently if this is not a error/warning report. this
is a *logic error* affect correctness which should be fixed.
for example, given the following .s
.syntax unified
.thumb
.type entry, %function
.global entry
entry:
blx label <=== A
.type label, %function
label:
bx lr
.arm
.type label2, %function
label2:
blx label3
.type label3, %function
label3:
bx lr
as -o 1.o 1.s
objdump -d 1.o
00000000 <entry>:
0: f7ff fffe bl 0 <entry>
at location A, a detected it's a thumb->thumb blx, then we convert it to bl, but the relocated
destination point to itself which is wrong. this bug is just caused by mixed use of cpu_variant
and selected_cpu.
this patch and the following tries to clean up all the wrong usage of selected_cpu, to make
feature check be consistent in the assembler.
New variable usage
=======================
* the first patch tries the following variable renaming:
s/cpu_variant/parse_arch/
s/selected_cpu_name/intended_arch_name/
s/selected_cpu/intended_arch/
* the second patch update intended_arch based on the info we got
during parsing, and thus naturally fix this bug.
"parse_arch" are to be used during gas parsing stage, for example those
do_XXX encoder in tc-arm.c.
"intended_arch" are to be used during all stage after parsing.
new variable calculation logic is:
* intended_arch default to be arm_arch_none which is empty.
* intended_arch initialized to the value of arch if any of
them is specified by cmdline or directive.
* if (inteneded_arch not empty) then
parse_arch = intended_arch
else
parse_arch = accept_all
the idea behind is if none arch info specified by the user, then
we should be permissive in parsing stage, while be strict in later
fixup stage. because accept unsupported instructions in parsing stage
will normally cause ill-instruction exception on silicon which is
obvious for user to fix, while wrong relocations may introduce silent
bugs which is hard to hunt.
any comments on this ?
thanks.
gas/
* config/tc-arm.c : Rename "cpu_variant" to "parse_arch",
"selected_cpu" to intended_arch", "selected_cpu_name" to
"intended_arch_name"
From 0ecc9c5ce28d7f7546ad5368e0b9a8916d576f5d Mon Sep 17 00:00:00 2001
From: Jiong Wang <jiong.wang@arm.com>
Date: Tue, 12 Aug 2014 10:05:59 +0100
Subject: [PATCH 1/2] [ARM/GAS] Rename two internal variables.
s/cpu_variant/parse_arch/
s/selected_cpu/intended_arch/
*no functional change*
---
gas/config/tc-arm.c | 236 +++++++++++++++++++++++++--------------------------
1 file changed, 118 insertions(+), 118 deletions(-)
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 7dc0e7e..5760b77 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -123,7 +123,7 @@ enum arm_float_abi
#define streq(a, b) (strcmp (a, b) == 0)
-static arm_feature_set cpu_variant;
+static arm_feature_set parse_arch;
static arm_feature_set arm_arch_used;
static arm_feature_set thumb_arch_used;
@@ -245,16 +245,16 @@ static const arm_feature_set crc_ext_armv8 =
static int mfloat_abi_opt = -1;
/* Record user cpu selection for object attributes. */
-static arm_feature_set selected_cpu = ARM_ARCH_NONE;
+static arm_feature_set intended_arch = ARM_ARCH_NONE;
/* Must be long enough to hold any of the names in arm_cpus. */
-static char selected_cpu_name[16];
+static char intended_arch_name[16];
/* Return if no cpu was selected on command-line. */
static bfd_boolean
no_cpu_selected (void)
{
- return selected_cpu.core == arm_arch_none.core
- && selected_cpu.coproc == arm_arch_none.coproc;
+ return intended_arch.core == arm_arch_none.core
+ && intended_arch.coproc == arm_arch_none.coproc;
}
#ifdef OBJ_ELF
@@ -1098,7 +1098,7 @@ md_atof (int type, char * litP, int * sizeP)
}
else
{
- if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
+ if (ARM_CPU_HAS_FEATURE (parse_arch, fpu_endian_pure))
for (i = prec - 1; i >= 0; i--)
{
md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
@@ -1777,7 +1777,7 @@ parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype)
if (etype != REGLIST_VFP_S)
{
/* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
- if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
+ if (ARM_CPU_HAS_FEATURE (parse_arch, fpu_vfp_ext_d32))
{
max_regs = 32;
if (thumb_mode)
@@ -2746,7 +2746,7 @@ opcode_select (int width)
case 16:
if (! thumb_mode)
{
- if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
+ if (!ARM_CPU_HAS_FEATURE (parse_arch, arm_ext_v4t))
as_bad (_("selected processor does not support THUMB opcodes"));
thumb_mode = 1;
@@ -2759,7 +2759,7 @@ opcode_select (int width)
case 32:
if (thumb_mode)
{
- if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
+ if (!ARM_CPU_HAS_FEATURE (parse_arch, arm_ext_v1))
as_bad (_("selected processor does not support ARM opcodes"));
thumb_mode = 0;
@@ -5729,12 +5729,12 @@ parse_psr (char **str, bfd_boolean lhs)
const struct asm_psr *psr;
char *start;
bfd_boolean is_apsr = FALSE;
- bfd_boolean m_profile = ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m);
+ bfd_boolean m_profile = ARM_CPU_HAS_FEATURE (intended_arch, arm_ext_m);
/* PR gas/12698: If the user has specified -march=all then m_profile will
be TRUE, but we want to ignore it in this case as we are building for any
CPU type, including non-m variants. */
- if (selected_cpu.core == arm_arch_any.core)
+ if (intended_arch.core == arm_arch_any.core)
m_profile = FALSE;
/* CPSR's and SPSR's can now be lowercase. This is just a convenience
@@ -5857,7 +5857,7 @@ check_suffix:
if (g_bit == 0x1)
{
- if (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp))
+ if (!ARM_CPU_HAS_FEATURE (intended_arch, arm_ext_v6_dsp))
{
inst.error = _("selected processor does not "
"support DSP extension");
@@ -6053,7 +6053,7 @@ static bfd_boolean
mark_feature_used (const arm_feature_set *feature)
{
/* Ensure the option is valid on the current architecture. */
- if (!ARM_CPU_HAS_FEATURE (cpu_variant, *feature))
+ if (!ARM_CPU_HAS_FEATURE (parse_arch, *feature))
return FALSE;
/* Add the appropriate architecture feature for the barrier option used.
@@ -6937,7 +6937,7 @@ parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
case OP_wPSR:
case OP_rPSR:
po_reg_or_goto (REG_TYPE_RNB, try_psr);
- if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_virt))
+ if (!ARM_CPU_HAS_FEATURE (parse_arch, arm_ext_virt))
{
inst.error = _("Banked registers are not available with this "
"architecture.");
@@ -7261,7 +7261,7 @@ encode_arm_vfp_reg (int reg, enum vfp_reg_pos pos)
if ((pos == VFP_REG_Dd || pos == VFP_REG_Dn || pos == VFP_REG_Dm)
&& reg > 15)
{
- if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
+ if (ARM_CPU_HAS_FEATURE (parse_arch, fpu_vfp_ext_d32))
{
if (thumb_mode)
ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
@@ -7433,7 +7433,7 @@ encode_arm_addr_mode_2 (int i, bfd_boolean is_t)
/* Use of PC in str is deprecated for ARMv7. */
if (warn_on_deprecated
&& !is_load
- && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7))
+ && ARM_CPU_HAS_FEATURE (intended_arch, arm_ext_v7))
as_warn (_("use of PC in this instruction is deprecated"));
}
@@ -7931,12 +7931,12 @@ do_rn_rd (void)
static bfd_boolean
check_obsolete (const arm_feature_set *feature, const char *msg)
{
- if (ARM_CPU_IS_ANY (cpu_variant))
+ if (ARM_CPU_IS_ANY (parse_arch))
{
as_warn ("%s", msg);
return TRUE;
}
- else if (ARM_CPU_HAS_FEATURE (cpu_variant, *feature))
+ else if (ARM_CPU_HAS_FEATURE (parse_arch, *feature))
{
as_bad ("%s", msg);
return TRUE;
@@ -7960,7 +7960,7 @@ do_rd_rm_rn (void)
if (!check_obsolete (&arm_ext_v8,
_("swp{b} use is obsoleted for ARMv8 and later"))
&& warn_on_deprecated
- && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6))
+ && ARM_CPU_HAS_FEATURE (parse_arch, arm_ext_v6))
as_warn (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
}
@@ -8205,7 +8205,7 @@ do_bx (void)
inst.instruction |= inst.operands[0].reg;
/* Output R_ARM_V4BX relocations if is an EABI object that looks like
it is for ARMv4t or earlier. */
- want_reloc = !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5);
+ want_reloc = !ARM_CPU_HAS_FEATURE (intended_arch, arm_ext_v5);
if (object_arch && !ARM_CPU_HAS_FEATURE (*object_arch, arm_ext_v5))
want_reloc = TRUE;
@@ -8335,9 +8335,9 @@ do_co_reg (void)
&& inst.operands[4].reg == r->crm
&& inst.operands[5].imm == r->opc2)
{
- if (! ARM_CPU_IS_ANY (cpu_variant)
+ if (! ARM_CPU_IS_ANY (parse_arch)
&& warn_on_deprecated
- && ARM_CPU_HAS_FEATURE (cpu_variant, r->deprecated))
+ && ARM_CPU_HAS_FEATURE (parse_arch, r->deprecated))
as_warn ("%s", r->dep_msg);
}
}
@@ -8687,7 +8687,7 @@ do_mlas (void)
{
/* This restriction does not apply to mls (nor to mla in v6 or later). */
if (inst.operands[0].reg == inst.operands[1].reg
- && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)
+ && !ARM_CPU_HAS_FEATURE (intended_arch, arm_ext_v6)
&& !(inst.instruction & 0x00400000))
as_tsktsk (_("Rd and Rm should be different in mla"));
@@ -8863,7 +8863,7 @@ do_mul (void)
inst.instruction |= inst.operands[2].reg << 8;
if (inst.operands[0].reg == inst.operands[1].reg
- && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
+ && !ARM_CPU_HAS_FEATURE (intended_arch, arm_ext_v6))
as_tsktsk (_("Rd and Rm should be different in mul"));
}
@@ -8888,7 +8888,7 @@ do_mull (void)
/* rdhi, rdlo and rm must all be different before armv6. */
if ((inst.operands[0].reg == inst.operands[2].reg
|| inst.operands[1].reg == inst.operands[2].reg)
- && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
+ && !ARM_CPU_HAS_FEATURE (intended_arch, arm_ext_v6))
as_tsktsk (_("rdhi, rdlo and rm must all be different"));
}
@@ -8896,7 +8896,7 @@ static void
do_nop (void)
{
if (inst.operands[0].present
- || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k))
+ || ARM_CPU_HAS_FEATURE (intended_arch, arm_ext_v6k))
{
/* Architectural NOP hints are CPSR sets with no bits selected. */
inst.instruction &= 0xf0000000;
@@ -9060,7 +9060,7 @@ static void
do_setend (void)
{
if (warn_on_deprecated
- && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
+ && ARM_CPU_HAS_FEATURE (parse_arch, arm_ext_v8))
as_warn (_("setend use is deprecated for ARMv8"));
if (inst.operands[0].imm)
@@ -9700,7 +9700,7 @@ static void
do_iwmmxt_wldstd (void)
{
inst.instruction |= inst.operands[0].reg << 12;
- if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2)
+ if (ARM_CPU_HAS_FEATURE (parse_arch, arm_cext_iwmmxt2)
&& inst.operands[1].immisreg)
{
inst.instruction &= ~0x1a000ff;
@@ -9743,7 +9743,7 @@ do_iwmmxt_wrwrwr_or_imm5 (void)
if (inst.operands[2].isreg)
do_rd_rn_rm ();
else {
- constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2),
+ constraint (!ARM_CPU_HAS_FEATURE (parse_arch, arm_cext_iwmmxt2),
_("immediate operand requires iWMMXt2"));
do_rd_rn ();
if (inst.operands[2].imm == 0)
@@ -10252,8 +10252,8 @@ do_t_add_sub (void)
/* Thumb-1 cores (except v6-M) require at least one high
register in a narrow non flag setting add. */
if (Rd > 7 || Rn > 7
- || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2)
- || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_msr))
+ || ARM_CPU_HAS_FEATURE (intended_arch, arm_ext_v6t2)
+ || ARM_CPU_HAS_FEATURE (intended_arch, arm_ext_msr))
{
if (Rd == Rn)
{
@@ -10820,7 +10820,7 @@ do_t_cpsi (void)
set_it_insn_type (OUTSIDE_IT_INSN);
if (unified_syntax
&& (inst.operands[1].present || inst.size_req == 4)
- && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6_notm))
+ && ARM_CPU_HAS_FEATURE (parse_arch, arm_ext_v6_notm))
{
unsigned int imod = (inst.instruction & 0x0030) >> 4;
inst.instruction = 0xf3af8000;
@@ -10831,7 +10831,7 @@ do_t_cpsi (void)
}
else
{
- constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)
+ constraint (!ARM_CPU_HAS_FEATURE (parse_arch, arm_ext_v1)
&& (inst.operands[0].imm & 4),
_("selected processor does not support 'A' form "
"of this instruction"));
@@ -11259,9 +11259,9 @@ do_t_ldst (void)
&& !inst.operands[1].immisreg)
{
if (no_cpu_selected ()
- || (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7)
- && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a)
- && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7r)))
+ || (ARM_CPU_HAS_FEATURE (parse_arch, arm_ext_v7)
+ && !ARM_CPU_HAS_FEATURE (parse_arch, arm_ext_v7a)
+ && !ARM_CPU_HAS_FEATURE (parse_arch, arm_ext_v7r)))
as_warn (_("This instruction may be unpredictable "
"if executed on M-profile cores "
"with interrupts enabled."));
@@ -11644,7 +11644,7 @@ do_t_mov_cmp (void)
results. Don't allow this. */
if (low_regs)
{
- constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6),
+ constraint (!ARM_CPU_HAS_FEATURE (parse_arch, arm_ext_v6),
"MOV Rd, Rs with two low registers is not "
"permitted on this architecture");
ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
@@ -11861,12 +11861,12 @@ do_t_mrs (void)
{
int flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
- if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
+ if (ARM_CPU_HAS_FEATURE (intended_arch, arm_ext_m))
{
/* PR gas/12698: The constraint is only applied for m_profile.
If the user has specified -march=all, we want to ignore it as
we are building for any CPU type, including non-m variants. */
- bfd_boolean m_profile = selected_cpu.core != arm_arch_any.core;
+ bfd_boolean m_profile = intended_arch.core != arm_arch_any.core;
constraint ((flags != 0) && m_profile, _("selected processor does "
"not support requested special purpose register"));
}
@@ -11899,17 +11899,17 @@ do_t_msr (void)
else
flags = inst.operands[0].imm;
- if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
+ if (ARM_CPU_HAS_FEATURE (intended_arch, arm_ext_m))
{
int bits = inst.operands[0].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
/* PR gas/12698: The constraint is only applied for m_profile.
If the user has specified -march=all, we want to ignore it as
we are building for any CPU type, including non-m variants. */
- bfd_boolean m_profile = selected_cpu.core != arm_arch_any.core;
- constraint (((ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
+ bfd_boolean m_profile = intended_arch.core != arm_arch_any.core;
+ constraint (((ARM_CPU_HAS_FEATURE (intended_arch, arm_ext_v6_dsp)
&& (bits & ~(PSR_s | PSR_f)) != 0)
- || (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
+ || (!ARM_CPU_HAS_FEATURE (intended_arch, arm_ext_v6_dsp)
&& bits != PSR_f)) && m_profile,
_("selected processor does not support requested special "
"purpose register"));
@@ -12031,7 +12031,7 @@ do_t_nop (void)
{
/* PR9722: Check for Thumb2 availability before
generating a thumb2 nop instruction. */
- if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2))
+ if (ARM_CPU_HAS_FEATURE (intended_arch, arm_ext_v6t2))
{
inst.instruction = THUMB_OP16 (inst.instruction);
inst.instruction |= inst.operands[0].imm << 4;
@@ -12327,7 +12327,7 @@ static void
do_t_setend (void)
{
if (warn_on_deprecated
- && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
+ && ARM_CPU_HAS_FEATURE (parse_arch, arm_ext_v8))
as_warn (_("setend use is deprecated for ARMv8"));
set_it_insn_type (OUTSIDE_IT_INSN);
@@ -12523,7 +12523,7 @@ static void
do_t_smc (void)
{
unsigned int value = inst.reloc.exp.X_add_number;
- constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a),
+ constraint (!ARM_CPU_HAS_FEATURE (parse_arch, arm_ext_v7a),
_("SMC is not permitted on this architecture"));
constraint (inst.reloc.exp.X_op != O_constant,
_("expression too complex"));
@@ -12699,11 +12699,11 @@ do_t_swi (void)
{
/* We have to do the following check manually as ARM_EXT_OS only applies
to ARM_EXT_V6M. */
- if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6m))
+ if (ARM_CPU_HAS_FEATURE (parse_arch, arm_ext_v6m))
{
- if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_os)
+ if (!ARM_CPU_HAS_FEATURE (parse_arch, arm_ext_os)
/* This only applies to the v6m howver, not later architectures. */
- && ! ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7))
+ && ! ARM_CPU_HAS_FEATURE (parse_arch, arm_ext_v7))
as_bad (_("SVC is not permitted on this architecture"));
ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, arm_ext_os);
}
@@ -13627,7 +13627,7 @@ do_vfp_nsyn_opcode (const char *opname)
if (!opcode)
abort ();
- constraint (!ARM_CPU_HAS_FEATURE (cpu_variant,
+ constraint (!ARM_CPU_HAS_FEATURE (parse_arch,
thumb_mode ? *opcode->tvariant : *opcode->avariant),
_(BAD_FPU));
@@ -15041,7 +15041,7 @@ do_neon_cvt_1 (enum neon_cvt_mode mode)
/* PR11109: Handle round-to-zero for VCVT conversions. */
if (mode == neon_cvt_mode_z
- && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_vfp_v2)
+ && ARM_CPU_HAS_FEATURE (parse_arch, fpu_arch_vfp_v2)
&& (flavour == neon_cvt_flavour_s32_f32
|| flavour == neon_cvt_flavour_u32_f32
|| flavour == neon_cvt_flavour_s32_f64
@@ -15683,9 +15683,9 @@ do_neon_mov (void)
et = neon_check_type (2, NS_NULL, N_8 | N_16 | N_32 | N_KEY, N_EQK);
logsize = neon_logbits (et.size);
- constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
+ constraint (!ARM_CPU_HAS_FEATURE (parse_arch, fpu_vfp_ext_v1),
_(BAD_FPU));
- constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
+ constraint (!ARM_CPU_HAS_FEATURE (parse_arch, fpu_neon_ext_v1)
&& et.size != 32, _(BAD_FPU));
constraint (et.type == NT_invtype, _("bad type for scalar"));
constraint (x >= 64 / et.size, _("scalar index out of range"));
@@ -15711,7 +15711,7 @@ do_neon_mov (void)
break;
case NS_DRR: /* case 5 (fmdrr). */
- constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
+ constraint (!ARM_CPU_HAS_FEATURE (parse_arch, fpu_vfp_ext_v2),
_(BAD_FPU));
inst.instruction = 0xc400b10;
@@ -15743,9 +15743,9 @@ do_neon_mov (void)
N_EQK, N_S8 | N_S16 | N_U8 | N_U16 | N_32 | N_KEY);
logsize = neon_logbits (et.size);
- constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
+ constraint (!ARM_CPU_HAS_FEATURE (parse_arch, fpu_vfp_ext_v1),
_(BAD_FPU));
- constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
+ constraint (!ARM_CPU_HAS_FEATURE (parse_arch, fpu_neon_ext_v1)
&& et.size != 32, _(BAD_FPU));
constraint (et.type == NT_invtype, _("bad type for scalar"));
constraint (x >= 64 / et.size, _("scalar index out of range"));
@@ -15770,7 +15770,7 @@ do_neon_mov (void)
break;
case NS_RRD: /* case 7 (fmrrd). */
- constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
+ constraint (!ARM_CPU_HAS_FEATURE (parse_arch, fpu_vfp_ext_v2),
_(BAD_FPU));
inst.instruction = 0xc500b10;
@@ -16020,7 +16020,7 @@ do_neon_ldr_str (void)
And is UNPREDICTABLE in thumb mode. */
if (!is_ldr
&& inst.operands[1].reg == REG_PC
- && (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7) || thumb_mode))
+ && (ARM_CPU_HAS_FEATURE (intended_arch, arm_ext_v7) || thumb_mode))
{
if (thumb_mode)
inst.error = _("Use of PC here is UNPREDICTABLE");
@@ -17283,7 +17283,7 @@ handle_it_state (void)
else
{
if ((implicit_it_mode & IMPLICIT_IT_MODE_THUMB)
- && ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2))
+ && ARM_CPU_HAS_FEATURE (parse_arch, arm_arch_t2))
{
/* Automatically generate the IT instruction. */
new_automatic_it_block (inst.cond);
@@ -17452,7 +17452,7 @@ it_fsm_post_encode (void)
if (now_it.insn_cond
&& !now_it.warn_deprecated
&& warn_on_deprecated
- && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
+ && ARM_CPU_HAS_FEATURE (parse_arch, arm_ext_v8))
{
if (inst.instruction >= 0x10000)
{
@@ -17555,7 +17555,7 @@ md_assemble (char *str)
{
arm_feature_set variant;
- variant = cpu_variant;
+ variant = parse_arch;
/* Only allow coprocessor instructions on Thumb-2 capable devices. */
if (!ARM_CPU_HAS_FEATURE (variant, arm_arch_t2))
ARM_CLEAR_FEATURE (variant, variant, fpu_any_hard);
@@ -17643,7 +17643,7 @@ md_assemble (char *str)
mapping_state (MAP_THUMB);
}
}
- else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
+ else if (ARM_CPU_HAS_FEATURE (parse_arch, arm_ext_v1))
{
bfd_boolean is_bx;
@@ -17653,7 +17653,7 @@ md_assemble (char *str)
/* Check that this instruction is supported for this CPU. */
if (!(is_bx && fix_v4bx)
&& !(opcode->avariant &&
- ARM_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant)))
+ ARM_CPU_HAS_FEATURE (parse_arch, *opcode->avariant)))
{
as_bad (_("selected processor does not support ARM mode `%s'"), str);
return;
@@ -20804,7 +20804,7 @@ arm_handle_align (fragS * fragP)
if (fragP->tc_frag_data.thumb_mode & (~ MODE_RECORDED))
{
- if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2))
+ if (ARM_CPU_HAS_FEATURE (intended_arch, arm_ext_v6t2))
{
narrow_noop = thumb_noop[1][target_big_endian];
noop = wide_thumb_noop[target_big_endian];
@@ -20818,7 +20818,7 @@ arm_handle_align (fragS * fragP)
}
else
{
- noop = arm_noop[ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k) != 0]
+ noop = arm_noop[ARM_CPU_HAS_FEATURE (intended_arch, arm_ext_v6k) != 0]
[target_big_endian];
noop_size = 4;
#ifdef OBJ_ELF
@@ -21435,7 +21435,7 @@ md_pcrel_from_section (fixS * fixP, segT seg)
&& (S_GET_SEGMENT (fixP->fx_addsy) == seg)
&& !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
&& ARM_IS_FUNC (fixP->fx_addsy)
- && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
+ && ARM_CPU_HAS_FEATURE (intended_arch, arm_ext_v5t))
base = fixP->fx_where + fixP->fx_frag->fr_address;
return base + 4;
@@ -21446,7 +21446,7 @@ md_pcrel_from_section (fixS * fixP, segT seg)
&& (S_GET_SEGMENT (fixP->fx_addsy) == seg)
&& !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
&& THUMB_IS_FUNC (fixP->fx_addsy)
- && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
+ && ARM_CPU_HAS_FEATURE (intended_arch, arm_ext_v5t))
base = fixP->fx_where + fixP->fx_frag->fr_address;
return (base + 4) & ~3;
@@ -21457,7 +21457,7 @@ md_pcrel_from_section (fixS * fixP, segT seg)
&& (S_GET_SEGMENT (fixP->fx_addsy) == seg)
&& !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
&& ARM_IS_FUNC (fixP->fx_addsy)
- && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
+ && ARM_CPU_HAS_FEATURE (intended_arch, arm_ext_v5t))
base = fixP->fx_where + fixP->fx_frag->fr_address;
return base + 8;
@@ -21466,7 +21466,7 @@ md_pcrel_from_section (fixS * fixP, segT seg)
&& (S_GET_SEGMENT (fixP->fx_addsy) == seg)
&& !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
&& THUMB_IS_FUNC (fixP->fx_addsy)
- && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
+ && ARM_CPU_HAS_FEATURE (intended_arch, arm_ext_v5t))
base = fixP->fx_where + fixP->fx_frag->fr_address;
return base + 8;
@@ -22296,7 +22296,7 @@ md_apply_fix (fixS * fixP,
#ifdef OBJ_ELF
case BFD_RELOC_ARM_PCREL_CALL:
- if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
+ if (ARM_CPU_HAS_FEATURE (intended_arch, arm_ext_v5t)
&& fixP->fx_addsy
&& !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
&& (S_GET_SEGMENT (fixP->fx_addsy) == seg)
@@ -22316,7 +22316,7 @@ md_apply_fix (fixS * fixP,
goto arm_branch_common;
case BFD_RELOC_ARM_PCREL_JUMP:
- if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
+ if (ARM_CPU_HAS_FEATURE (intended_arch, arm_ext_v5t)
&& fixP->fx_addsy
&& !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
&& (S_GET_SEGMENT (fixP->fx_addsy) == seg)
@@ -22339,7 +22339,7 @@ md_apply_fix (fixS * fixP,
case BFD_RELOC_ARM_PCREL_BLX:
temp = 1;
- if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
+ if (ARM_CPU_HAS_FEATURE (intended_arch, arm_ext_v5t)
&& fixP->fx_addsy
&& !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
&& (S_GET_SEGMENT (fixP->fx_addsy) == seg)
@@ -22447,7 +22447,7 @@ md_apply_fix (fixS * fixP,
&& (S_GET_SEGMENT (fixP->fx_addsy) == seg)
&& !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
&& ARM_IS_FUNC (fixP->fx_addsy)
- && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
+ && ARM_CPU_HAS_FEATURE (intended_arch, arm_ext_v5t))
{
/* Force a relocation for a branch 20 bits wide. */
fixP->fx_done = 0;
@@ -22507,7 +22507,7 @@ md_apply_fix (fixS * fixP,
&& (S_GET_SEGMENT (fixP->fx_addsy) == seg)
&& !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
&& ARM_IS_FUNC (fixP->fx_addsy)
- && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
+ && ARM_CPU_HAS_FEATURE (intended_arch, arm_ext_v5t))
{
newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
newval = newval & ~0x1000;
@@ -22533,7 +22533,7 @@ md_apply_fix (fixS * fixP,
if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff))
{
- if (!(ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2)))
+ if (!(ARM_CPU_HAS_FEATURE (parse_arch, arm_arch_t2)))
as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
else if ((value & ~0x1ffffff)
&& ((value & ~0x1ffffff) != ~0x1ffffff))
@@ -23745,9 +23745,9 @@ set_constant_flonums (void)
given architecture. */
static void
-autoselect_thumb_from_cpu_variant (void)
+autoselect_thumb_from_parse_arch (void)
{
- if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
+ if (!ARM_CPU_HAS_FEATURE (parse_arch, arm_ext_v1))
opcode_select (16);
}
@@ -23850,18 +23850,18 @@ md_begin (void)
if (!mcpu_cpu_opt)
{
mcpu_cpu_opt = &cpu_default;
- selected_cpu = cpu_default;
+ intended_arch = cpu_default;
}
#else
if (mcpu_cpu_opt)
- selected_cpu = *mcpu_cpu_opt;
+ intended_arch = *mcpu_cpu_opt;
else
mcpu_cpu_opt = &arm_arch_any;
#endif
- ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
+ ARM_MERGE_FEATURE_SETS (parse_arch, *mcpu_cpu_opt, *mfpu_opt);
- autoselect_thumb_from_cpu_variant ();
+ autoselect_thumb_from_parse_arch ();
arm_arch_used = thumb_arch_used = arm_arch_none;
@@ -23881,7 +23881,7 @@ md_begin (void)
if (support_interwork) flags |= F_INTERWORK;
if (uses_apcs_float) flags |= F_APCS_FLOAT;
if (pic_code) flags |= F_PIC;
- if (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_any_hard))
+ if (!ARM_CPU_HAS_FEATURE (parse_arch, fpu_any_hard))
flags |= F_SOFT_FLOAT;
switch (mfloat_abi_opt)
@@ -23898,11 +23898,11 @@ md_begin (void)
}
/* Using pure-endian doubles (even if soft-float). */
- if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
+ if (ARM_CPU_HAS_FEATURE (parse_arch, fpu_endian_pure))
flags |= F_VFP_FLOAT;
#if defined OBJ_ELF
- if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_maverick))
+ if (ARM_CPU_HAS_FEATURE (parse_arch, fpu_arch_maverick))
flags |= EF_ARM_MAVERICK_FLOAT;
break;
@@ -23938,37 +23938,37 @@ md_begin (void)
#endif
/* Record the CPU type as well. */
- if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2))
+ if (ARM_CPU_HAS_FEATURE (parse_arch, arm_cext_iwmmxt2))
mach = bfd_mach_arm_iWMMXt2;
- else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt))
+ else if (ARM_CPU_HAS_FEATURE (parse_arch, arm_cext_iwmmxt))
mach = bfd_mach_arm_iWMMXt;
- else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_xscale))
+ else if (ARM_CPU_HAS_FEATURE (parse_arch, arm_cext_xscale))
mach = bfd_mach_arm_XScale;
- else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_maverick))
+ else if (ARM_CPU_HAS_FEATURE (parse_arch, arm_cext_maverick))
mach = bfd_mach_arm_ep9312;
- else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5e))
+ else if (ARM_CPU_HAS_FEATURE (parse_arch, arm_ext_v5e))
mach = bfd_mach_arm_5TE;
- else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5))
+ else if (ARM_CPU_HAS_FEATURE (parse_arch, arm_ext_v5))
{
- if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
+ if (ARM_CPU_HAS_FEATURE (parse_arch, arm_ext_v4t))
mach = bfd_mach_arm_5T;
else
mach = bfd_mach_arm_5;
}
- else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4))
+ else if (ARM_CPU_HAS_FEATURE (parse_arch, arm_ext_v4))
{
- if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
+ if (ARM_CPU_HAS_FEATURE (parse_arch, arm_ext_v4t))
mach = bfd_mach_arm_4T;
else
mach = bfd_mach_arm_4;
}
- else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3m))
+ else if (ARM_CPU_HAS_FEATURE (parse_arch, arm_ext_v3m))
mach = bfd_mach_arm_3M;
- else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3))
+ else if (ARM_CPU_HAS_FEATURE (parse_arch, arm_ext_v3))
mach = bfd_mach_arm_3;
- else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2s))
+ else if (ARM_CPU_HAS_FEATURE (parse_arch, arm_ext_v2s))
mach = bfd_mach_arm_2a;
- else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2))
+ else if (ARM_CPU_HAS_FEATURE (parse_arch, arm_ext_v2))
mach = bfd_mach_arm_2;
else
mach = bfd_mach_arm_unknown;
@@ -24713,14 +24713,14 @@ arm_parse_cpu (char *str)
mcpu_cpu_opt = &opt->value;
mcpu_fpu_opt = &opt->default_fpu;
if (opt->canonical_name)
- strcpy (selected_cpu_name, opt->canonical_name);
+ strcpy (intended_arch_name, opt->canonical_name);
else
{
size_t i;
for (i = 0; i < len; i++)
- selected_cpu_name[i] = TOUPPER (opt->name[i]);
- selected_cpu_name[i] = 0;
+ intended_arch_name[i] = TOUPPER (opt->name[i]);
+ intended_arch_name[i] = 0;
}
if (ext != NULL)
@@ -24756,7 +24756,7 @@ arm_parse_arch (char *str)
{
march_cpu_opt = &opt->value;
march_fpu_opt = &opt->default_fpu;
- strcpy (selected_cpu_name, opt->name);
+ strcpy (intended_arch_name, opt->name);
if (ext != NULL)
return arm_parse_extension (ext, &march_cpu_opt);
@@ -25057,7 +25057,7 @@ aeabi_set_public_attributes (void)
(if any) and/or the instructions actually used. */
ARM_MERGE_FEATURE_SETS (flags, arm_arch_used, thumb_arch_used);
ARM_MERGE_FEATURE_SETS (flags, flags, *mfpu_opt);
- ARM_MERGE_FEATURE_SETS (flags, flags, selected_cpu);
+ ARM_MERGE_FEATURE_SETS (flags, flags, intended_arch);
if (ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any))
ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v1);
@@ -25104,11 +25104,11 @@ aeabi_set_public_attributes (void)
arch = 13;
/* Tag_CPU_name. */
- if (selected_cpu_name[0])
+ if (intended_arch_name[0])
{
char *q;
- q = selected_cpu_name;
+ q = intended_arch_name;
if (strncmp (q, "armv", 4) == 0)
{
int i;
@@ -25265,18 +25265,18 @@ s_arm_cpu (int ignored ATTRIBUTE_UNUSED)
if (streq (opt->name, name))
{
mcpu_cpu_opt = &opt->value;
- selected_cpu = opt->value;
+ intended_arch = opt->value;
if (opt->canonical_name)
- strcpy (selected_cpu_name, opt->canonical_name);
+ strcpy (intended_arch_name, opt->canonical_name);
else
{
int i;
for (i = 0; opt->name[i]; i++)
- selected_cpu_name[i] = TOUPPER (opt->name[i]);
+ intended_arch_name[i] = TOUPPER (opt->name[i]);
- selected_cpu_name[i] = 0;
+ intended_arch_name[i] = 0;
}
- ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
+ ARM_MERGE_FEATURE_SETS (parse_arch, *mcpu_cpu_opt, *mfpu_opt);
*input_line_pointer = saved_char;
demand_empty_rest_of_line ();
return;
@@ -25307,9 +25307,9 @@ s_arm_arch (int ignored ATTRIBUTE_UNUSED)
if (streq (opt->name, name))
{
mcpu_cpu_opt = &opt->value;
- selected_cpu = opt->value;
- strcpy (selected_cpu_name, opt->name);
- ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
+ intended_arch = opt->value;
+ strcpy (intended_arch_name, opt->name);
+ ARM_MERGE_FEATURE_SETS (parse_arch, *mcpu_cpu_opt, *mfpu_opt);
*input_line_pointer = saved_char;
demand_empty_rest_of_line ();
return;
@@ -25385,12 +25385,12 @@ s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED)
}
if (adding_value)
- ARM_MERGE_FEATURE_SETS (selected_cpu, selected_cpu, opt->value);
+ ARM_MERGE_FEATURE_SETS (intended_arch, intended_arch, opt->value);
else
- ARM_CLEAR_FEATURE (selected_cpu, selected_cpu, opt->value);
+ ARM_CLEAR_FEATURE (intended_arch, intended_arch, opt->value);
- mcpu_cpu_opt = &selected_cpu;
- ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
+ mcpu_cpu_opt = &intended_arch;
+ ARM_MERGE_FEATURE_SETS (parse_arch, *mcpu_cpu_opt, *mfpu_opt);
*input_line_pointer = saved_char;
demand_empty_rest_of_line ();
return;
@@ -25422,7 +25422,7 @@ s_arm_fpu (int ignored ATTRIBUTE_UNUSED)
if (streq (opt->name, name))
{
mfpu_opt = &opt->value;
- ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
+ ARM_MERGE_FEATURE_SETS (parse_arch, *mcpu_cpu_opt, *mfpu_opt);
*input_line_pointer = saved_char;
demand_empty_rest_of_line ();
return;
@@ -25524,7 +25524,7 @@ int
arm_apply_sym_value (struct fix * fixP)
{
if (fixP->fx_addsy
- && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
+ && ARM_CPU_HAS_FEATURE (intended_arch, arm_ext_v5t)
&& !S_FORCE_RELOC (fixP->fx_addsy, TRUE))
{
switch (fixP->fx_r_type)
--
1.7.9.5