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RE: [PATCH] Add support for MIPS eretnc MIPS32r5 instruction
- From: Andrew Bennett <Andrew dot Bennett at imgtec dot com>
- To: Richard Sandiford <rdsandiford at googlemail dot com>
- Cc: "binutils at sourceware dot org" <binutils at sourceware dot org>, Matthew Fortune <Matthew dot Fortune at imgtec dot com>, Saeed Ghazanfar <Saeed dot Ghazanfar at imgtec dot com>, Rich Fuhler <Rich dot Fuhler at imgtec dot com>
- Date: Thu, 1 May 2014 16:21:06 +0000
- Subject: RE: [PATCH] Add support for MIPS eretnc MIPS32r5 instruction
- Authentication-results: sourceware.org; auth=none
- References: <0DA23CC379F5F945ACB41CF394B9827755A9EA at LEMAIL01 dot le dot imgtec dot org> <87wqegw90k dot fsf at sandifor-thinkpad dot stglab dot manchester dot uk dot ibm dot com> <0DA23CC379F5F945ACB41CF394B98277574ADA at LEMAIL01 dot le dot imgtec dot org>
>>Andrew Bennett <Andrew.Bennett@imgtec.com> writes:
>>> This patch adds support for the eretnc MIPS32r5 instruction. For more
>>> information on the instruction please refer to:
>>> http://www.imgtec.com/powervr/insider/powervr-login.asp?doc=MD00087v6
>>>
>>> The patch and ChangeLog entry are shown below.
>>
>> This is the first time that we've distinguished between r2 and r5 in the
>> base ISA, so at this point I think we really do need to make binutils aware
>> of r5 as a separate architecture revision, rather than adding it to r2.
>> It'd probably make sense to add r3 at the same time, since it seems odd
>> to have r5 without r3.
>>
>> It's OK to mark the output as r2 for now, since that's the best we have.
>> Matthew's changes should let us fix it up later. But we should model r5
>> separately in the user interface and internally.
>
> Thats fine. I will rework the patch and then post it back on the list.
The updated patch and ChangeLog is below.
Regards,
Andrew
2014-05-01 Andrew Bennett <andrew.bennett@imgtec.com>
bfd/
* aoutx.h (NAME (aout, machine_type)): Add mips32r3, mips64r3,
mips32r5 and mips64r5.
* archures.c (bfd_architecture): Likewise.
* bfd-in2.h (bfd_architecture): Likewise.
* cpu-mips.c (arch_info_struct): Likewise.
* elfxx-mips.c (mips_set_isa_flags): Likewise.
gas/
* tc-mips.c (ISA_SUPPORTS_MIPS16E): Add mips32r3, mips32r5, mips64r3
and mips64r5.
(ISA_HAS_64BIT_FPRS): Likewise.
(ISA_HAS_ROR): Likewise.
(ISA_HAS_ODD_SINGLE_FPR): Likewise.
(ISA_HAS_MXHC1): Likewise.
(hilo_interlocks): Likewise.
(md_longopts): Likewise.
(ISA_HAS_64BIT_REGS): Add mips64r3 and mips64r5.
(ISA_HAS_DROR): Likewise.
(options): Add OPTION_MIPS32R3, OPTION_MIPS32R5, OPTION_MIPS64R3, and
OPTION_MIPS64R5.
(mips_isa_rev): Add support for mips32r3, mips32r5, mips64r3 and
mips64r5.
(md_parse_option): Likewise.
(s_mipsset): Likewise.
(mips_cpu_info_table): Add entries for mips32r3, mips32r5, mips64r3
and mips64r5. Also change p5600 entry to be mips32r5.
* configure.in: Add support for mips32r3, mips32r5, mips64r3 and
mips64r5.
* configure: Regenerate.
* doc/c-mips.texi: Document the -mips32r3, -mips32r5, -mips64r3 and
-mips64r5 command line options.
gas/testsuite/
* gas/mips/mips.exp: Add MIPS32r5 tests. Also add the mips32r3,
mips32r5, mips64r3 and mips64r5 isas to the testsuite.
* gas/mips/r5.s: New test.
* gas/mips/r5.d: Likewise.
include/opcode/
* mips.h (INSN_ISA_MASK): Updated.
(INSN_ISA32R3): New define.
(INSN_ISA32R5): New define.
(INSN_ISA64R3): New define.
(INSN_ISA64R5): New define.
(mips_isa_table): Add entries for mips32r3, mips32r5, mips64r3 and
mips64r5.
(ISA_MIPS32R3): New define.
(ISA_MIPS32R5): New define.
(ISA_MIPS64R3): New define.
(ISA_MIPS64R5): New define.
(CPU_MIPS32R3): New define.
(CPU_MIPS32R5): New define.
(CPU_MIPS64R3): New define.
(CPU_MIPS64R5): New define.
opcodes/
* mips-opc.c (mips_builtin_opcodes): Add MIPS32r5 eretnc instruction.
(I34): New define.
(I35): New define.
(I66): New define.
(I67): New define.
* mips-dis.c (mips_arch_choices): Add mips32r3, mips32r5, mips64r3 and
mips64r5.
(parse_mips_dis_option): Update MSA and virtualization support to
allow mips64r3 and mips64r5.
diff --git a/bfd/aoutx.h b/bfd/aoutx.h
index ad81a7a..1e23bca 100644
--- a/bfd/aoutx.h
+++ b/bfd/aoutx.h
@@ -791,9 +791,13 @@ NAME (aout, machine_type) (enum bfd_architecture arch,
case bfd_mach_mips16:
case bfd_mach_mipsisa32:
case bfd_mach_mipsisa32r2:
+ case bfd_mach_mipsisa32r3:
+ case bfd_mach_mipsisa32r5:
case bfd_mach_mips5:
case bfd_mach_mipsisa64:
case bfd_mach_mipsisa64r2:
+ case bfd_mach_mipsisa64r3:
+ case bfd_mach_mipsisa64r5:
case bfd_mach_mips_sb1:
case bfd_mach_mips_xlr:
/* FIXME: These should be MIPS3, MIPS4, MIPS16, MIPS32, etc. */
diff --git a/bfd/archures.c b/bfd/archures.c
index 4ab5f1d..20e4d0b 100644
--- a/bfd/archures.c
+++ b/bfd/archures.c
@@ -182,8 +182,12 @@ DESCRIPTION
.#define bfd_mach_mips_xlr 887682 {* decimal 'XLR' *}
.#define bfd_mach_mipsisa32 32
.#define bfd_mach_mipsisa32r2 33
+.#define bfd_mach_mipsisa32r3 34
+.#define bfd_mach_mipsisa32r5 35
.#define bfd_mach_mipsisa64 64
.#define bfd_mach_mipsisa64r2 65
+.#define bfd_mach_mipsisa64r3 66
+.#define bfd_mach_mipsisa64r5 67
.#define bfd_mach_mips_micromips 96
. bfd_arch_i386, {* Intel 386 *}
.#define bfd_mach_i386_intel_syntax (1 << 0)
diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
index e38441c..7212e75 100644
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
@@ -1967,8 +1967,12 @@ enum bfd_architecture
#define bfd_mach_mips_xlr 887682 /* decimal 'XLR' */
#define bfd_mach_mipsisa32 32
#define bfd_mach_mipsisa32r2 33
+#define bfd_mach_mipsisa32r3 34
+#define bfd_mach_mipsisa32r5 35
#define bfd_mach_mipsisa64 64
#define bfd_mach_mipsisa64r2 65
+#define bfd_mach_mipsisa64r3 66
+#define bfd_mach_mipsisa64r5 67
#define bfd_mach_mips_micromips 96
bfd_arch_i386, /* Intel 386 */
#define bfd_mach_i386_intel_syntax (1 << 0)
diff --git a/bfd/cpu-mips.c b/bfd/cpu-mips.c
index 6e5a787..360049c 100644
--- a/bfd/cpu-mips.c
+++ b/bfd/cpu-mips.c
@@ -87,8 +87,12 @@ enum
I_mips5,
I_mipsisa32,
I_mipsisa32r2,
+ I_mipsisa32r3,
+ I_mipsisa32r5,
I_mipsisa64,
I_mipsisa64r2,
+ I_mipsisa64r3,
+ I_mipsisa64r5,
I_sb1,
I_loongson_2e,
I_loongson_2f,
@@ -131,8 +135,12 @@ static const bfd_arch_info_type arch_info_struct[] =
N (64, 64, bfd_mach_mips5, "mips:mips5", FALSE, NN(I_mips5)),
N (32, 32, bfd_mach_mipsisa32, "mips:isa32", FALSE, NN(I_mipsisa32)),
N (32, 32, bfd_mach_mipsisa32r2,"mips:isa32r2", FALSE, NN(I_mipsisa32r2)),
+ N (32, 32, bfd_mach_mipsisa32r3,"mips:isa32r3", FALSE, NN(I_mipsisa32r3)),
+ N (32, 32, bfd_mach_mipsisa32r5,"mips:isa32r5", FALSE, NN(I_mipsisa32r5)),
N (64, 64, bfd_mach_mipsisa64, "mips:isa64", FALSE, NN(I_mipsisa64)),
N (64, 64, bfd_mach_mipsisa64r2,"mips:isa64r2", FALSE, NN(I_mipsisa64r2)),
+ N (64, 64, bfd_mach_mipsisa64r3,"mips:isa64r3", FALSE, NN(I_mipsisa64r3)),
+ N (64, 64, bfd_mach_mipsisa64r5,"mips:isa64r5", FALSE, NN(I_mipsisa64r5)),
N (64, 64, bfd_mach_mips_sb1, "mips:sb1", FALSE, NN(I_sb1)),
N (64, 64, bfd_mach_mips_loongson_2e, "mips:loongson_2e", FALSE, NN(I_loongson_2e)),
N (64, 64, bfd_mach_mips_loongson_2f, "mips:loongson_2f", FALSE, NN(I_loongson_2f)),
diff --git a/bfd/elfxx-mips.c b/bfd/elfxx-mips.c
index d939444..5e16e52 100644
--- a/bfd/elfxx-mips.c
+++ b/bfd/elfxx-mips.c
@@ -11664,10 +11664,14 @@ mips_set_isa_flags (bfd *abfd)
break;
case bfd_mach_mipsisa32r2:
+ case bfd_mach_mipsisa32r3:
+ case bfd_mach_mipsisa32r5:
val = E_MIPS_ARCH_32R2;
break;
case bfd_mach_mipsisa64r2:
+ case bfd_mach_mipsisa64r3:
+ case bfd_mach_mipsisa64r5:
val = E_MIPS_ARCH_64R2;
break;
}
diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
index 960169e..1c950a7 100644
--- a/gas/config/tc-mips.c
+++ b/gas/config/tc-mips.c
@@ -306,8 +306,12 @@ static int file_ase_mips16;
#define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
|| mips_opts.isa == ISA_MIPS32R2 \
+ || mips_opts.isa == ISA_MIPS32R3 \
+ || mips_opts.isa == ISA_MIPS32R5 \
|| mips_opts.isa == ISA_MIPS64 \
- || mips_opts.isa == ISA_MIPS64R2)
+ || mips_opts.isa == ISA_MIPS64R2 \
+ || mips_opts.isa == ISA_MIPS64R3 \
+ || mips_opts.isa == ISA_MIPS64R5)
/* True if any microMIPS code was produced. */
static int file_ase_micromips;
@@ -351,7 +355,9 @@ static int mips_32bitmode = 0;
|| (ISA) == ISA_MIPS4 \
|| (ISA) == ISA_MIPS5 \
|| (ISA) == ISA_MIPS64 \
- || (ISA) == ISA_MIPS64R2)
+ || (ISA) == ISA_MIPS64R2 \
+ || (ISA) == ISA_MIPS64R3 \
+ || (ISA) == ISA_MIPS64R5)
/* Return true if ISA supports 64 bit wide float registers. */
#define ISA_HAS_64BIT_FPRS(ISA) \
@@ -359,13 +365,19 @@ static int mips_32bitmode = 0;
|| (ISA) == ISA_MIPS4 \
|| (ISA) == ISA_MIPS5 \
|| (ISA) == ISA_MIPS32R2 \
+ || (ISA) == ISA_MIPS32R3 \
+ || (ISA) == ISA_MIPS32R5 \
|| (ISA) == ISA_MIPS64 \
- || (ISA) == ISA_MIPS64R2)
+ || (ISA) == ISA_MIPS64R2 \
+ || (ISA) == ISA_MIPS64R3 \
+ || (ISA) == ISA_MIPS64R5 )
/* Return true if ISA supports 64-bit right rotate (dror et al.)
instructions. */
#define ISA_HAS_DROR(ISA) \
((ISA) == ISA_MIPS64R2 \
+ || (ISA) == ISA_MIPS64R3 \
+ || (ISA) == ISA_MIPS64R5 \
|| (mips_opts.micromips \
&& ISA_HAS_64BIT_REGS (ISA)) \
)
@@ -374,7 +386,11 @@ static int mips_32bitmode = 0;
instructions. */
#define ISA_HAS_ROR(ISA) \
((ISA) == ISA_MIPS32R2 \
+ || (ISA) == ISA_MIPS32R3 \
+ || (ISA) == ISA_MIPS32R5 \
|| (ISA) == ISA_MIPS64R2 \
+ || (ISA) == ISA_MIPS64R3 \
+ || (ISA) == ISA_MIPS64R5 \
|| (mips_opts.ase & ASE_SMARTMIPS) \
|| mips_opts.micromips \
)
@@ -383,14 +399,22 @@ static int mips_32bitmode = 0;
#define ISA_HAS_ODD_SINGLE_FPR(ISA) \
((ISA) == ISA_MIPS32 \
|| (ISA) == ISA_MIPS32R2 \
+ || (ISA) == ISA_MIPS32R3 \
+ || (ISA) == ISA_MIPS32R5 \
|| (ISA) == ISA_MIPS64 \
- || (ISA) == ISA_MIPS64R2)
+ || (ISA) == ISA_MIPS64R2 \
+ || (ISA) == ISA_MIPS64R3 \
+ || (ISA) == ISA_MIPS64R5)
/* Return true if ISA supports move to/from high part of a 64-bit
floating-point register. */
#define ISA_HAS_MXHC1(ISA) \
((ISA) == ISA_MIPS32R2 \
- || (ISA) == ISA_MIPS64R2)
+ || (ISA) == ISA_MIPS32R3 \
+ || (ISA) == ISA_MIPS32R5 \
+ || (ISA) == ISA_MIPS64R2 \
+ || (ISA) == ISA_MIPS64R3 \
+ || (ISA) == ISA_MIPS64R5)
#define HAVE_32BIT_GPRS \
(mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
@@ -473,8 +497,12 @@ static int mips_32bitmode = 0;
#define hilo_interlocks \
(mips_opts.isa == ISA_MIPS32 \
|| mips_opts.isa == ISA_MIPS32R2 \
+ || mips_opts.isa == ISA_MIPS32R3 \
+ || mips_opts.isa == ISA_MIPS32R5 \
|| mips_opts.isa == ISA_MIPS64 \
|| mips_opts.isa == ISA_MIPS64R2 \
+ || mips_opts.isa == ISA_MIPS64R3 \
+ || mips_opts.isa == ISA_MIPS64R5 \
|| mips_opts.arch == CPU_R4010 \
|| mips_opts.arch == CPU_R5900 \
|| mips_opts.arch == CPU_R10000 \
@@ -1317,7 +1345,11 @@ enum options
OPTION_MIPS32,
OPTION_MIPS64,
OPTION_MIPS32R2,
+ OPTION_MIPS32R3,
+ OPTION_MIPS32R5,
OPTION_MIPS64R2,
+ OPTION_MIPS64R3,
+ OPTION_MIPS64R5,
OPTION_MIPS16,
OPTION_NO_MIPS16,
OPTION_MIPS3D,
@@ -1422,7 +1454,11 @@ struct option md_longopts[] =
{"mips32", no_argument, NULL, OPTION_MIPS32},
{"mips64", no_argument, NULL, OPTION_MIPS64},
{"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
+ {"mips32r3", no_argument, NULL, OPTION_MIPS32R3},
+ {"mips32r5", no_argument, NULL, OPTION_MIPS32R5},
{"mips64r2", no_argument, NULL, OPTION_MIPS64R2},
+ {"mips64r3", no_argument, NULL, OPTION_MIPS64R3},
+ {"mips64r5", no_argument, NULL, OPTION_MIPS64R5},
/* Options which specify Application Specific Extensions (ASEs). */
{"mips16", no_argument, NULL, OPTION_MIPS16},
@@ -1861,6 +1897,12 @@ mips_isa_rev (void)
if (mips_opts.isa == ISA_MIPS32R2 || mips_opts.isa == ISA_MIPS64R2)
return 2;
+ if (mips_opts.isa == ISA_MIPS32R3 || mips_opts.isa == ISA_MIPS64R3)
+ return 3;
+
+ if (mips_opts.isa == ISA_MIPS32R5 || mips_opts.isa == ISA_MIPS64R5)
+ return 5;
+
/* microMIPS implies revision 2 or above. */
if (mips_opts.micromips)
return 2;
@@ -13533,10 +13575,26 @@ md_parse_option (int c, char *arg)
file_mips_isa = ISA_MIPS32R2;
break;
+ case OPTION_MIPS32R3:
+ file_mips_isa = ISA_MIPS32R3;
+ break;
+
+ case OPTION_MIPS32R5:
+ file_mips_isa = ISA_MIPS32R5;
+ break;
+
case OPTION_MIPS64R2:
file_mips_isa = ISA_MIPS64R2;
break;
+ case OPTION_MIPS64R3:
+ file_mips_isa = ISA_MIPS64R3;
+ break;
+
+ case OPTION_MIPS64R5:
+ file_mips_isa = ISA_MIPS64R5;
+ break;
+
case OPTION_MIPS64:
file_mips_isa = ISA_MIPS64;
break;
@@ -15089,6 +15147,8 @@ s_mipsset (int x ATTRIBUTE_UNUSED)
case ISA_MIPS2:
case ISA_MIPS32:
case ISA_MIPS32R2:
+ case ISA_MIPS32R3:
+ case ISA_MIPS32R5:
mips_opts.gp32 = 1;
mips_opts.fp32 = 1;
break;
@@ -15097,6 +15157,8 @@ s_mipsset (int x ATTRIBUTE_UNUSED)
case ISA_MIPS5:
case ISA_MIPS64:
case ISA_MIPS64R2:
+ case ISA_MIPS64R3:
+ case ISA_MIPS64R5:
mips_opts.gp32 = 0;
if (mips_opts.arch == CPU_R5900)
{
@@ -17806,8 +17868,12 @@ static const struct mips_cpu_info mips_cpu_info_table[] =
{ "mips5", MIPS_CPU_IS_ISA, 0, ISA_MIPS5, CPU_MIPS5 },
{ "mips32", MIPS_CPU_IS_ISA, 0, ISA_MIPS32, CPU_MIPS32 },
{ "mips32r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
+ { "mips32r3", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R3, CPU_MIPS32R3 },
+ { "mips32r5", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R5, CPU_MIPS32R5 },
{ "mips64", MIPS_CPU_IS_ISA, 0, ISA_MIPS64, CPU_MIPS64 },
{ "mips64r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R2, CPU_MIPS64R2 },
+ { "mips64r3", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R3, CPU_MIPS64R3 },
+ { "mips64r5", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R5, CPU_MIPS64R5 },
/* MIPS I */
{ "r3000", 0, 0, ISA_MIPS1, CPU_R3000 },
@@ -17911,7 +17977,7 @@ static const struct mips_cpu_info mips_cpu_info_table[] =
{ "1004kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
{ "1004kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
/* P5600 with EVA and Virtualization ASEs, other ASEs are optional. */
- { "p5600", 0, ASE_VIRT | ASE_EVA | ASE_XPA, ISA_MIPS32R2, CPU_MIPS32R2 },
+ { "p5600", 0, ASE_VIRT | ASE_EVA | ASE_XPA, ISA_MIPS32R5, CPU_MIPS32R5 },
/* MIPS 64 */
{ "5kc", 0, 0, ISA_MIPS64, CPU_MIPS64 },
@@ -18120,8 +18186,12 @@ MIPS options:\n\
-mips5 generate MIPS ISA V instructions\n\
-mips32 generate MIPS32 ISA instructions\n\
-mips32r2 generate MIPS32 release 2 ISA instructions\n\
+-mips32r3 generate MIPS32 release 3 ISA instructions\n\
+-mips32r5 generate MIPS32 release 5 ISA instructions\n\
-mips64 generate MIPS64 ISA instructions\n\
-mips64r2 generate MIPS64 release 2 ISA instructions\n\
+-mips64r3 generate MIPS64 release 3 ISA instructions\n\
+-mips64r5 generate MIPS64 release 5 ISA instructions\n\
-march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
first = 1;
diff --git a/gas/configure b/gas/configure
index 27b9d1d..2530377 100755
--- a/gas/configure
+++ b/gas/configure
@@ -12036,12 +12036,24 @@ _ACEOF
mipsisa32r2 | mipsisa32r2el)
mips_cpu=mips32r2
;;
+ mipsisa32r3 | mipsisa32r3el)
+ mips_cpu=mips32r3
+ ;;
+ mipsisa32r5 | mipsisa32r5el)
+ mips_cpu=mips32r5
+ ;;
mipsisa64 | mipsisa64el)
mips_cpu=mips64
;;
mipsisa64r2 | mipsisa64r2el)
mips_cpu=mips64r2
;;
+ mipsisa64r3 | mipsisa64r3el)
+ mips_cpu=mips64r3
+ ;;
+ mipsisa64r5 | mipsisa64r5el)
+ mips_cpu=mips64r5
+ ;;
mipstx39 | mipstx39el)
mips_cpu=r3900
;;
diff --git a/gas/configure.in b/gas/configure.in
index 33cd50b..b9f9a98 100644
--- a/gas/configure.in
+++ b/gas/configure.in
@@ -213,12 +213,24 @@ changequote([,])dnl
mipsisa32r2 | mipsisa32r2el)
mips_cpu=mips32r2
;;
+ mipsisa32r3 | mipsisa32r3el)
+ mips_cpu=mips32r3
+ ;;
+ mipsisa32r5 | mipsisa32r5el)
+ mips_cpu=mips32r5
+ ;;
mipsisa64 | mipsisa64el)
mips_cpu=mips64
;;
mipsisa64r2 | mipsisa64r2el)
mips_cpu=mips64r2
;;
+ mipsisa64r3 | mipsisa64r3el)
+ mips_cpu=mips64r3
+ ;;
+ mipsisa64r5 | mipsisa64r5el)
+ mips_cpu=mips64r5
+ ;;
mipstx39 | mipstx39el)
mips_cpu=r3900
;;
diff --git a/gas/doc/c-mips.texi b/gas/doc/c-mips.texi
index 0c5e82d..e940ba3 100644
--- a/gas/doc/c-mips.texi
+++ b/gas/doc/c-mips.texi
@@ -81,16 +81,22 @@ VxWorks-style position-independent macro expansions.
@itemx -mips5
@itemx -mips32
@itemx -mips32r2
+@itemx -mips32r5
+@itemx -mips32r6
@itemx -mips64
@itemx -mips64r2
+@itemx -mips64r5
+@itemx -mips64r6
Generate code for a particular MIPS Instruction Set Architecture level.
@samp{-mips1} corresponds to the R2000 and R3000 processors,
@samp{-mips2} to the R6000 processor, @samp{-mips3} to the
R4000 processor, and @samp{-mips4} to the R8000 and R10000 processors.
-@samp{-mips5}, @samp{-mips32}, @samp{-mips32r2}, @samp{-mips64}, and
-@samp{-mips64r2} correspond to generic MIPS V, MIPS32, MIPS32 Release 2,
-MIPS64, and MIPS64 Release 2 ISA processors, respectively. You can also
-switch instruction sets during the assembly; see @ref{MIPS ISA,
+@samp{-mips5}, @samp{-mips32}, @samp{-mips32r2}, @samp{-mips32r3},
+@samp{-mips32r5}, @samp{-mips64}, @samp{-mips64r2}, @samp{-mips64r3}, and
+@samp{-mips64r5} correspond to generic MIPS V, MIPS32, MIPS32 Release 2,
+MIPS32 Release 3, MIPS32 Release 5, MIPS64, and MIPS64 Release 2,
+MIPS64 Release 3 and MIPS64 Release 5 ISA processors, respectively. You can
+also switch instruction sets during the assembly; see @ref{MIPS ISA,
Directives to override the ISA level}.
@item -mgp32
@@ -652,8 +658,8 @@ Small data is not supported for SVR4-style PIC.
@kindex @code{.set mips@var{n}}
@sc{gnu} @code{@value{AS}} supports an additional directive to change
the MIPS Instruction Set Architecture level on the fly: @code{.set
-mips@var{n}}. @var{n} should be a number from 0 to 5, or 32, 32r2, 64
-or 64r2.
+mips@var{n}}. @var{n} should be a number from 0 to 5, or 32, 32r2, 32r3,
+32r5, 64, 64r2, 64r3 or 64r5.
The values other than 0 make the assembler accept instructions
for the corresponding ISA level, from that point on in the
assembly. @code{.set mips@var{n}} affects not only which instructions
diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp
index b0d8ac2..9da95c6 100644
--- a/gas/testsuite/gas/mips/mips.exp
+++ b/gas/testsuite/gas/mips/mips.exp
@@ -416,6 +416,14 @@ mips_arch_create mips32r2 32 mips32 { fpisa3 fpisa4 fpisa5 ror } \
{ -march=mips32r2 -mtune=mips32r2 } \
{ -mmips:isa32r2 } \
{ mipsisa32r2-*-* mipsisa32r2el-*-* }
+mips_arch_create mips32r3 32 mips32r2 { fpisa3 fpisa4 fpisa5 ror } \
+ { -march=mips32r3 -mtune=mips32r3 } \
+ { -mmips:isa32r3 } \
+ { mipsisa32r3-*-* mipsisa32r3el-*-* }
+mips_arch_create mips32r5 32 mips32r3 { fpisa3 fpisa4 fpisa5 ror } \
+ { -march=mips32r5 -mtune=mips32r5 } \
+ { -mmips:isa32r5 } \
+ { mipsisa32r5-*-* mipsisa32r5el-*-* }
mips_arch_create mips64 64 mips5 { mips32 } \
{ -march=mips64 -mtune=mips64 } { -mmips:isa64 } \
{ mipsisa64-*-* mipsisa64el-*-* }
@@ -423,6 +431,14 @@ mips_arch_create mips64r2 64 mips64 { mips32r2 ror } \
{ -march=mips64r2 -mtune=mips64r2 } \
{ -mmips:isa64r2 } \
{ mipsisa64r2-*-* mipsisa64r2el-*-* }
+mips_arch_create mips64r3 64 mips64r2 { mips32r3 ror } \
+ { -march=mips64r3 -mtune=mips64r3 } \
+ { -mmips:isa64r3 } \
+ { mipsisa64r3-*-* mipsisa64r3el-*-* }
+mips_arch_create mips64r5 64 mips64r3 { mips32r5 ror } \
+ { -march=mips64r5 -mtune=mips64r5 } \
+ { -mmips:isa64r5 } \
+ { mipsisa64r5-*-* mipsisa64r5el-*-* }
mips_arch_create mips16 32 {} {} \
{ -march=mips1 -mips16 } { -mmips:16 }
mips_arch_create micromips 64 mips64r2 {} \
@@ -1171,6 +1187,7 @@ if { [istarget mips*-*-vxworks*] } {
run_dump_test_arches "msa-branch" [mips_arch_list_matching mips32r2]
run_dump_test_arches "xpa" [mips_arch_list_matching mips32r2 !micromips]
+ run_dump_test_arches "r5" [mips_arch_list_matching mips32r5 !micromips]
run_dump_test "pcrel-1"
run_dump_test "pcrel-2"
diff --git a/gas/testsuite/gas/mips/r5.d b/gas/testsuite/gas/mips/r5.d
new file mode 100644
index 0000000..d1073fe
--- /dev/null
+++ b/gas/testsuite/gas/mips/r5.d
@@ -0,0 +1,8 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: Test MIPS32r5 instructions
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 42000058 eretnc
+ ...
diff --git a/gas/testsuite/gas/mips/r5.s b/gas/testsuite/gas/mips/r5.s
new file mode 100644
index 0000000..12260d3
--- /dev/null
+++ b/gas/testsuite/gas/mips/r5.s
@@ -0,0 +1,10 @@
+ .text
+ .set noat
+ .set noreorder
+ .set nomacro
+test_r5:
+ eretnc
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 2
+ .space 8
diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index a5d2935..d032b1c 100644
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -1058,7 +1058,7 @@ struct mips_opcode
word constructed using these macros is a bitmask of the remaining
INSN_* values below. */
-#define INSN_ISA_MASK 0x0000000ful
+#define INSN_ISA_MASK 0x0000001ful
/* We cannot start at zero due to ISA_UNKNOWN below. */
#define INSN_ISA1 1
@@ -1079,6 +1079,10 @@ struct mips_opcode
#define INSN_ISA4_32 12
#define INSN_ISA4_32R2 13
#define INSN_ISA5_32R2 14
+#define INSN_ISA32R3 15
+#define INSN_ISA32R5 16
+#define INSN_ISA64R3 17
+#define INSN_ISA64R5 18
/* Given INSN_ISA* values X and Y, where X ranges over INSN_ISA1 through
INSN_ISA5_32R2 and Y ranges over INSN_ISA1 through INSN_ISA64R2,
@@ -1089,7 +1093,8 @@ struct mips_opcode
(mips_isa_table[(Y & INSN_ISA_MASK) - 1] >> ((X & INSN_ISA_MASK) - 1)) & 1
is non-zero. */
static const unsigned int mips_isa_table[] =
- { 0x0001, 0x0003, 0x0607, 0x1e0f, 0x3e1f, 0x0a23, 0x3e63, 0x3ebf, 0x3fff };
+ { 0x0001, 0x0003, 0x0607, 0x1e0f, 0x3e1f, 0x0a23, 0x3e63, 0x3ebf, 0x3fff,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x7e63, 0xfe63, 0x17fff, 0x3ffff };
/* Masks used for Chip specific instructions. */
#define INSN_CHIP_MASK 0xc3ff0f20
@@ -1171,7 +1176,11 @@ static const unsigned int mips_isa_table[] =
#define ISA_MIPS64 INSN_ISA64
#define ISA_MIPS32R2 INSN_ISA32R2
+#define ISA_MIPS32R3 INSN_ISA32R3
+#define ISA_MIPS32R5 INSN_ISA32R5
#define ISA_MIPS64R2 INSN_ISA64R2
+#define ISA_MIPS64R3 INSN_ISA64R3
+#define ISA_MIPS64R5 INSN_ISA64R5
/* CPU defines, use instead of hardcoding processor number. Keep this
@@ -1203,9 +1212,13 @@ static const unsigned int mips_isa_table[] =
#define CPU_MIPS16 16
#define CPU_MIPS32 32
#define CPU_MIPS32R2 33
+#define CPU_MIPS32R3 34
+#define CPU_MIPS32R5 35
#define CPU_MIPS5 5
#define CPU_MIPS64 64
#define CPU_MIPS64R2 65
+#define CPU_MIPS64R3 66
+#define CPU_MIPS64R5 67
#define CPU_SB1 12310201 /* octal 'SB', 01. */
#define CPU_LOONGSON_2E 3001
#define CPU_LOONGSON_2F 3002
diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c
index 0f8624e..b797e5d 100644
--- a/opcodes/mips-dis.c
+++ b/opcodes/mips-dis.c
@@ -556,6 +556,22 @@ const struct mips_arch_choice mips_arch_choices[] =
mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 },
+ { "mips32r3", 1, bfd_mach_mipsisa32r3, CPU_MIPS32R3,
+ ISA_MIPS32R3,
+ (ASE_SMARTMIPS | ASE_DSP | ASE_DSPR2 | ASE_EVA | ASE_MIPS3D
+ | ASE_MT | ASE_MCU | ASE_VIRT | ASE_MSA | ASE_XPA),
+ mips_cp0_names_mips3264r2,
+ mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
+ mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 },
+
+ { "mips32r5", 1, bfd_mach_mipsisa32r5, CPU_MIPS32R5,
+ ISA_MIPS32R5,
+ (ASE_SMARTMIPS | ASE_DSP | ASE_DSPR2 | ASE_EVA | ASE_MIPS3D
+ | ASE_MT | ASE_MCU | ASE_VIRT | ASE_MSA | ASE_XPA),
+ mips_cp0_names_mips3264r2,
+ mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
+ mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 },
+
/* For stock MIPS64, disassemble all applicable MIPS-specified ASEs. */
{ "mips64", 1, bfd_mach_mipsisa64, CPU_MIPS64,
ISA_MIPS64, ASE_MIPS3D | ASE_MDMX,
@@ -571,6 +587,22 @@ const struct mips_arch_choice mips_arch_choices[] =
mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 },
+ { "mips64r3", 1, bfd_mach_mipsisa64r3, CPU_MIPS64R3,
+ ISA_MIPS64R3,
+ (ASE_MIPS3D | ASE_DSP | ASE_DSPR2 | ASE_DSP64 | ASE_EVA | ASE_MT
+ | ASE_MCU | ASE_VIRT | ASE_VIRT64 | ASE_MSA | ASE_MSA64 | ASE_XPA),
+ mips_cp0_names_mips3264r2,
+ mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
+ mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 },
+
+ { "mips64r5", 1, bfd_mach_mipsisa64r5, CPU_MIPS64R5,
+ ISA_MIPS64R5,
+ (ASE_MIPS3D | ASE_DSP | ASE_DSPR2 | ASE_DSP64 | ASE_EVA | ASE_MT
+ | ASE_MCU | ASE_VIRT | ASE_VIRT64 | ASE_MSA | ASE_MSA64 | ASE_XPA),
+ mips_cp0_names_mips3264r2,
+ mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
+ mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 },
+
{ "sb1", 1, bfd_mach_mips_sb1, CPU_SB1,
ISA_MIPS64 | INSN_SB1, ASE_MIPS3D,
mips_cp0_names_sb1,
@@ -798,7 +830,9 @@ parse_mips_dis_option (const char *option, unsigned int len)
if (CONST_STRNEQ (option, "msa"))
{
mips_ase |= ASE_MSA;
- if ((mips_isa & INSN_ISA_MASK) == ISA_MIPS64R2)
+ if ((mips_isa & INSN_ISA_MASK) == ISA_MIPS64R2
+ || (mips_isa & INSN_ISA_MASK) == ISA_MIPS64R3
+ || (mips_isa & INSN_ISA_MASK) == ISA_MIPS64R5)
mips_ase |= ASE_MSA64;
return;
}
@@ -806,7 +840,9 @@ parse_mips_dis_option (const char *option, unsigned int len)
if (CONST_STRNEQ (option, "virt"))
{
mips_ase |= ASE_VIRT;
- if (mips_isa & ISA_MIPS64R2)
+ if (mips_isa & ISA_MIPS64R2
+ || mips_isa & ISA_MIPS64R3
+ || mips_isa & ISA_MIPS64R5)
mips_ase |= ASE_VIRT64;
return;
}
diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index 9181c3f..4d54517 100644
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -249,7 +249,11 @@ decode_mips_operand (const char *p)
#define I32 INSN_ISA32
#define I64 INSN_ISA64
#define I33 INSN_ISA32R2
+#define I34 INSN_ISA32R3
+#define I35 INSN_ISA32R5
#define I65 INSN_ISA64R2
+#define I66 INSN_ISA64R3
+#define I67 INSN_ISA64R5
#define I3_32 INSN_ISA3_32
#define I3_33 INSN_ISA3_32R2
#define I4_32 INSN_ISA4_32
@@ -1093,6 +1097,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"emt", "", 0x41600be1, 0xffffffff, TRAP, 0, 0, MT32, 0 },
{"emt", "t", 0x41600be1, 0xffe0ffff, WR_1|TRAP, 0, 0, MT32, 0 },
{"eret", "", 0x42000018, 0xffffffff, NODS, 0, I3_32, 0, 0 },
+{"eretnc", "", 0x42000058, 0xffffffff, NODS, 0, I35, 0, 0 },
{"evpe", "", 0x41600021, 0xffffffff, TRAP, 0, 0, MT32, 0 },
{"evpe", "t", 0x41600021, 0xffe0ffff, WR_1|TRAP, 0, 0, MT32, 0 },
{"ext", "t,r,+A,+C", 0x7c000000, 0xfc00003f, WR_1|RD_2, 0, I33, 0, 0 },
--
1.7.1