This is the mail archive of the
binutils@sourceware.org
mailing list for the binutils project.
Re: Changing the MIPS ISA definition for the Loongson 3A from MIPS64 to MIPS64r2
- From: Richard Sandiford <rdsandiford at googlemail dot com>
- To: Heiher <r at hev dot cc>
- Cc: Andrew Bennett <Andrew dot Bennett at imgtec dot com>, "binutils\ at sourceware dot org" <binutils at sourceware dot org>
- Date: Tue, 04 Mar 2014 21:18:37 +0000
- Subject: Re: Changing the MIPS ISA definition for the Loongson 3A from MIPS64 to MIPS64r2
- Authentication-results: sourceware.org; auth=none
- References: <0DA23CC379F5F945ACB41CF394B98277531609 at LEMAIL01 dot le dot imgtec dot org> <87d2i78awj dot fsf at sandifor-thinkpad dot stglab dot manchester dot uk dot ibm dot com> <CAHirt9imQwZYrV7Miwu-Wbb9fYppHDmha+MVVrMtmQWYipd6pQ at mail dot gmail dot com> <87d2i6cqfw dot fsf at talisman dot default> <CAHirt9g8-t6H9Jy4-wPYs4Ep2uXd+sdE-VafNZbqmKQT3MW41A at mail dot gmail dot com>
Heiher <r@hev.cc> writes:
> In Arch Linux MIPS N32 port, Most packages build with "-march=mips64r2 -mtune=
> loongson3a" to compatible with other MIPS64R2 platforms. Some popular apps
> (performance is a concern, e.g. firefox 17.0.1 and mozjs 17.0.0 ...) are
> compiled with "-march=loongson3a" instaed of "-march=mips64r2 -mtune=
> loongson3a", they works well, too.
OK, thanks. I found I needed the first patch below too in order for
instructions like GSMOD to be disassembled correctly. Without it they'd
be disassembled as UDI instead.
Here's what I installed -- sorry for the delay.
Thanks,
Richard
opcodes/
* mips-opc.c (mips_builtin_opcodes): Move the udi* instructions
so that they come after the Loongson extensions.
bfd/
2014-02-04 Heiher <r@hev.cc>
* elfxx-mips.c (mips_set_isa_flags): Use E_MIPS_ARCH_64R2 for
Loongson-3A.
(mips_mach_extensions): Make bfd_mach_mips_loongson_3a an
extension of bfd_mach_mipsisa64r2.
opcodes/
2014-02-04 Heiher <r@hev.cc>
* mips-dis.c (mips_arch_choices): Usee ISA_MIPS64R2 for Loongson-3A.
gas/
2014-02-04 Heiher <r@hev.cc>
* config/tc-mips.c (mips_cpu_info_table): Use ISA_MIPS64R2 for
Loongson-3A.
Index: opcodes/mips-opc.c
===================================================================
--- opcodes/mips-opc.c 2014-03-04 21:13:29.248857461 +0000
+++ opcodes/mips-opc.c 2014-03-04 21:13:29.342858274 +0000
@@ -1956,72 +1956,6 @@ const struct mips_opcode mips_builtin_op
{"zcb", "(b)", 0x7000071f, 0xfc1fffff, RD_1|SM, 0, IOCT2, 0, 0 },
{"zcbt", "(b)", 0x7000075f, 0xfc1fffff, RD_1|SM, 0, IOCT2, 0, 0 },
-/* User Defined Instruction. */
-{"udi0", "s,t,d,+1", 0x70000010, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi0", "s,t,+2", 0x70000010, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi0", "s,+3", 0x70000010, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi0", "+4", 0x70000010, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi1", "s,t,d,+1", 0x70000011, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi1", "s,t,+2", 0x70000011, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi1", "s,+3", 0x70000011, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi1", "+4", 0x70000011, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi2", "s,t,d,+1", 0x70000012, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi2", "s,t,+2", 0x70000012, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi2", "s,+3", 0x70000012, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi2", "+4", 0x70000012, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi3", "s,t,d,+1", 0x70000013, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi3", "s,t,+2", 0x70000013, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi3", "s,+3", 0x70000013, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi3", "+4", 0x70000013, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi4", "s,t,d,+1", 0x70000014, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi4", "s,t,+2", 0x70000014, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi4", "s,+3", 0x70000014, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi4", "+4", 0x70000014, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi5", "s,t,d,+1", 0x70000015, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi5", "s,t,+2", 0x70000015, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi5", "s,+3", 0x70000015, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi5", "+4", 0x70000015, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi6", "s,t,d,+1", 0x70000016, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi6", "s,t,+2", 0x70000016, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi6", "s,+3", 0x70000016, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi6", "+4", 0x70000016, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi7", "s,t,d,+1", 0x70000017, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi7", "s,t,+2", 0x70000017, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi7", "s,+3", 0x70000017, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi7", "+4", 0x70000017, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi8", "s,t,d,+1", 0x70000018, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi8", "s,t,+2", 0x70000018, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi8", "s,+3", 0x70000018, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi8", "+4", 0x70000018, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi9", "s,t,d,+1", 0x70000019, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi9", "s,t,+2", 0x70000019, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi9", "s,+3", 0x70000019, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi9", "+4", 0x70000019, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi10", "s,t,d,+1", 0x7000001a, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi10", "s,t,+2", 0x7000001a, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi10", "s,+3", 0x7000001a, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi10", "+4", 0x7000001a, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi11", "s,t,d,+1", 0x7000001b, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi11", "s,t,+2", 0x7000001b, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi11", "s,+3", 0x7000001b, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi11", "+4", 0x7000001b, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi12", "s,t,d,+1", 0x7000001c, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi12", "s,t,+2", 0x7000001c, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi12", "s,+3", 0x7000001c, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi12", "+4", 0x7000001c, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi13", "s,t,d,+1", 0x7000001d, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi13", "s,t,+2", 0x7000001d, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi13", "s,+3", 0x7000001d, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi13", "+4", 0x7000001d, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi14", "s,t,d,+1", 0x7000001e, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi14", "s,t,+2", 0x7000001e, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi14", "s,+3", 0x7000001e, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi14", "+4", 0x7000001e, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi15", "s,t,d,+1", 0x7000001f, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi15", "s,t,+2", 0x7000001f, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi15", "s,+3", 0x7000001f, 0xfc00003f, UDI, 0, I33, 0, 0 },
-{"udi15", "+4", 0x7000001f, 0xfc00003f, UDI, 0, I33, 0, 0 },
-
/* Coprocessor 2 move/branch operations overlap with VR5400 .ob format
instructions so they are here for the latters to take precedence. */
{"bc2f", "p", 0x49000000, 0xffff0000, RD_CC|CBD, 0, I1, 0, IOCT|IOCTP|IOCT2 },
@@ -3103,6 +3037,72 @@ const struct mips_opcode mips_builtin_op
{"move.v", "+d,+e", 0x78be0019, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
{"lsa", "d,v,t,+~", 0x00000005, 0xfc00073f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
{"dlsa", "d,v,t,+~", 0x00000015, 0xfc00073f, WR_1|RD_2|RD_3, 0, 0, MSA64, 0 },
+
+/* User Defined Instruction. */
+{"udi0", "s,t,d,+1", 0x70000010, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi0", "s,t,+2", 0x70000010, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi0", "s,+3", 0x70000010, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi0", "+4", 0x70000010, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi1", "s,t,d,+1", 0x70000011, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi1", "s,t,+2", 0x70000011, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi1", "s,+3", 0x70000011, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi1", "+4", 0x70000011, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi2", "s,t,d,+1", 0x70000012, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi2", "s,t,+2", 0x70000012, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi2", "s,+3", 0x70000012, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi2", "+4", 0x70000012, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi3", "s,t,d,+1", 0x70000013, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi3", "s,t,+2", 0x70000013, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi3", "s,+3", 0x70000013, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi3", "+4", 0x70000013, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi4", "s,t,d,+1", 0x70000014, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi4", "s,t,+2", 0x70000014, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi4", "s,+3", 0x70000014, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi4", "+4", 0x70000014, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi5", "s,t,d,+1", 0x70000015, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi5", "s,t,+2", 0x70000015, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi5", "s,+3", 0x70000015, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi5", "+4", 0x70000015, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi6", "s,t,d,+1", 0x70000016, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi6", "s,t,+2", 0x70000016, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi6", "s,+3", 0x70000016, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi6", "+4", 0x70000016, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi7", "s,t,d,+1", 0x70000017, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi7", "s,t,+2", 0x70000017, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi7", "s,+3", 0x70000017, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi7", "+4", 0x70000017, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi8", "s,t,d,+1", 0x70000018, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi8", "s,t,+2", 0x70000018, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi8", "s,+3", 0x70000018, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi8", "+4", 0x70000018, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi9", "s,t,d,+1", 0x70000019, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi9", "s,t,+2", 0x70000019, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi9", "s,+3", 0x70000019, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi9", "+4", 0x70000019, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi10", "s,t,d,+1", 0x7000001a, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi10", "s,t,+2", 0x7000001a, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi10", "s,+3", 0x7000001a, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi10", "+4", 0x7000001a, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi11", "s,t,d,+1", 0x7000001b, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi11", "s,t,+2", 0x7000001b, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi11", "s,+3", 0x7000001b, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi11", "+4", 0x7000001b, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi12", "s,t,d,+1", 0x7000001c, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi12", "s,t,+2", 0x7000001c, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi12", "s,+3", 0x7000001c, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi12", "+4", 0x7000001c, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi13", "s,t,d,+1", 0x7000001d, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi13", "s,t,+2", 0x7000001d, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi13", "s,+3", 0x7000001d, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi13", "+4", 0x7000001d, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi14", "s,t,d,+1", 0x7000001e, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi14", "s,t,+2", 0x7000001e, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi14", "s,+3", 0x7000001e, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi14", "+4", 0x7000001e, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi15", "s,t,d,+1", 0x7000001f, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi15", "s,t,+2", 0x7000001f, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi15", "s,+3", 0x7000001f, 0xfc00003f, UDI, 0, I33, 0, 0 },
+{"udi15", "+4", 0x7000001f, 0xfc00003f, UDI, 0, I33, 0, 0 },
/* No hazard protection on coprocessor instructions--they shouldn't
change the state of the processor and if they do it's up to the
user to put in nops as necessary. These are at the end so that the
Index: bfd/elfxx-mips.c
===================================================================
--- bfd/elfxx-mips.c 2014-03-04 18:34:43.596004152 +0000
+++ bfd/elfxx-mips.c 2014-03-04 18:34:51.714069288 +0000
@@ -11624,7 +11624,7 @@ mips_set_isa_flags (bfd *abfd)
break;
case bfd_mach_mips_loongson_3a:
- val = E_MIPS_ARCH_64 | E_MIPS_MACH_LS3A;
+ val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_LS3A;
break;
case bfd_mach_mips_octeon:
@@ -14208,12 +14208,12 @@ static const struct mips_mach_extension
{ bfd_mach_mips_octeon2, bfd_mach_mips_octeonp },
{ bfd_mach_mips_octeonp, bfd_mach_mips_octeon },
{ bfd_mach_mips_octeon, bfd_mach_mipsisa64r2 },
+ { bfd_mach_mips_loongson_3a, bfd_mach_mipsisa64r2 },
/* MIPS64 extensions. */
{ bfd_mach_mipsisa64r2, bfd_mach_mipsisa64 },
{ bfd_mach_mips_sb1, bfd_mach_mipsisa64 },
{ bfd_mach_mips_xlr, bfd_mach_mipsisa64 },
- { bfd_mach_mips_loongson_3a, bfd_mach_mipsisa64 },
/* MIPS V extensions. */
{ bfd_mach_mipsisa64, bfd_mach_mips5 },
Index: opcodes/mips-dis.c
===================================================================
--- opcodes/mips-dis.c 2014-03-04 18:34:43.596004152 +0000
+++ opcodes/mips-dis.c 2014-03-04 18:35:56.237584913 +0000
@@ -588,7 +588,7 @@ const struct mips_arch_choice mips_arch_
NULL, 0, mips_cp1_names_numeric, mips_hwr_names_numeric },
{ "loongson3a", 1, bfd_mach_mips_loongson_3a, CPU_LOONGSON_3A,
- ISA_MIPS64 | INSN_LOONGSON_3A, 0, mips_cp0_names_numeric,
+ ISA_MIPS64R2 | INSN_LOONGSON_3A, 0, mips_cp0_names_numeric,
NULL, 0, mips_cp1_names_mips3264, mips_hwr_names_numeric },
{ "octeon", 1, bfd_mach_mips_octeon, CPU_OCTEON,
Index: gas/config/tc-mips.c
===================================================================
--- gas/config/tc-mips.c 2014-03-04 18:34:43.596004152 +0000
+++ gas/config/tc-mips.c 2014-03-04 18:34:51.717069312 +0000
@@ -17904,7 +17904,7 @@ static const struct mips_cpu_info mips_c
/* Broadcom SB-1A CPU core */
{ "sb1a", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 },
- { "loongson3a", 0, 0, ISA_MIPS64, CPU_LOONGSON_3A },
+ { "loongson3a", 0, 0, ISA_MIPS64R2, CPU_LOONGSON_3A },
/* MIPS 64 Release 2 */