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Re: Minor tweaks to the MIPS documentation
- From: "Maciej W. Rozycki" <macro at codesourcery dot com>
- To: Richard Sandiford <rdsandiford at googlemail dot com>
- Cc: Eli Zaretskii <eliz at gnu dot org>, <binutils at sourceware dot org>
- Date: Wed, 26 Jun 2013 13:16:45 +0100
- Subject: Re: Minor tweaks to the MIPS documentation
- References: <87a9mi5d8l dot fsf at talisman dot default> <alpine dot DEB dot 1 dot 10 dot 1306252252320 dot 16287 at tp dot orcam dot me dot uk> <87y59x2xvi dot fsf at talisman dot default>
On Wed, 26 Jun 2013, Richard Sandiford wrote:
> > @@ -91,8 +91,8 @@ R4000 processor, and @samp{-mips4} to th
> > R10000 processors. @samp{-mips5}, @samp{-mips32}, @samp{-mips32r2},
> > @samp{-mips64}, and @samp{-mips64r2}
> > correspond to generic
> > -@sc{MIPS V}, @sc{MIPS32}, @sc{MIPS32 Release 2}, @sc{MIPS64},
> > -and @sc{MIPS64 Release 2}
> > +@samp{MIPS V}, @samp{MIPS32}, @samp{MIPS32 Release 2}, @samp{MIPS64},
> > +and @samp{MIPS64 Release 2}
> > ISA processors, respectively. You can also switch
> > instruction sets during the assembly; see @ref{MIPS ISA, Directives to
> > override the ISA level}.
>
> As Eli says, using @samp here is wrong. Please just remove the @sc instead.
>
> OK with that change, thanks.
Here's the version I applied, thanks for your review.
2013-06-26 Maciej W. Rozycki <macro@codesourcery.com>
gas/
* doc/as.texinfo (Overview): Remove @samp from MIPS ISA names.
* doc/c-mips.texi (MIPS Options): Remove @sc from MIPS ISA names.
Replace @sc{mips16} with literal `MIPS16'.
(MIPS ISA): Replace @sc{mips3} with literal `MIPS III'.
Maciej
binutils-mips-gas-doc-sc.diff
Index: binutils-fsf-trunk-quilt/gas/doc/as.texinfo
===================================================================
--- binutils-fsf-trunk-quilt.orig/gas/doc/as.texinfo 2013-06-25 01:09:04.000000000 +0100
+++ binutils-fsf-trunk-quilt/gas/doc/as.texinfo 2013-06-26 10:59:00.729948346 +0100
@@ -1253,11 +1253,8 @@ Generate code for a particular MIPS Inst
alias for @samp{-march=r6000}, @samp{-mips3} is an alias for
@samp{-march=r4000} and @samp{-mips4} is an alias for @samp{-march=r8000}.
@samp{-mips5}, @samp{-mips32}, @samp{-mips32r2}, @samp{-mips64}, and
-@samp{-mips64r2}
-correspond to generic
-@samp{MIPS V}, @samp{MIPS32}, @samp{MIPS32 Release 2}, @samp{MIPS64},
-and @samp{MIPS64 Release 2}
-ISA processors, respectively.
+@samp{-mips64r2} correspond to generic MIPS V, MIPS32, MIPS32 Release 2,
+MIPS64, and MIPS64 Release 2 ISA processors, respectively.
@item -march=@var{cpu}
Generate code for a particular MIPS CPU.
Index: binutils-fsf-trunk-quilt/gas/doc/c-mips.texi
===================================================================
--- binutils-fsf-trunk-quilt.orig/gas/doc/c-mips.texi 2013-06-25 01:09:04.000000000 +0100
+++ binutils-fsf-trunk-quilt/gas/doc/c-mips.texi 2013-06-26 11:05:01.251203430 +0100
@@ -87,15 +87,12 @@ VxWorks-style position-independent macro
Generate code for a particular MIPS Instruction Set Architecture level.
@samp{-mips1} corresponds to the R2000 and R3000 processors,
@samp{-mips2} to the R6000 processor, @samp{-mips3} to the
-R4000 processor, and @samp{-mips4} to the R8000 and
-R10000 processors. @samp{-mips5}, @samp{-mips32}, @samp{-mips32r2},
-@samp{-mips64}, and @samp{-mips64r2}
-correspond to generic
-@sc{MIPS V}, @sc{MIPS32}, @sc{MIPS32 Release 2}, @sc{MIPS64},
-and @sc{MIPS64 Release 2}
-ISA processors, respectively. You can also switch
-instruction sets during the assembly; see @ref{MIPS ISA, Directives to
-override the ISA level}.
+R4000 processor, and @samp{-mips4} to the R8000 and R10000 processors.
+@samp{-mips5}, @samp{-mips32}, @samp{-mips32r2}, @samp{-mips64}, and
+@samp{-mips64r2} correspond to generic MIPS V, MIPS32, MIPS32 Release 2,
+MIPS64, and MIPS64 Release 2 ISA processors, respectively. You can also
+switch instruction sets during the assembly; see @ref{MIPS ISA,
+Directives to override the ISA level}.
@item -mgp32
@itemx -mfp32
@@ -414,7 +411,7 @@ be relaxed with the use of a longer sequ
however this has not been implemented and if their target turns out of
reach, they produce an error even if branch relaxation is enabled.
-Also no @sc{mips16} branches are ever relaxed.
+Also no MIPS16 branches are ever relaxed.
By default @samp{--no-relax-branch} is selected, causing any out-of-range
branches to produce an error.
@@ -636,7 +633,7 @@ assembly. @code{.set mips@var{n}} affec
are permitted, but also how certain macros are expanded. @code{.set
mips0} restores the @sc{isa} level to its original level: either the
level you selected with command line options, or the default for your
-configuration. You can use this feature to permit specific @sc{mips3}
+configuration. You can use this feature to permit specific MIPS III
instructions while assembling in 32 bit mode. Use this directive with
care!