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[Patch, AArch64] Add support for CRC instructions
- From: Yufeng Zhang <Yufeng dot Zhang at arm dot com>
- To: "binutils at sourceware dot org" <binutils at sourceware dot org>
- Cc: Marcus Shawcroft <Marcus dot Shawcroft at arm dot com>
- Date: Tue, 26 Feb 2013 20:46:14 +0000
- Subject: [Patch, AArch64] Add support for CRC instructions
Hi,
This patch adds support for the CRC instructions in the AArch64 GAS and
disassembler. OK for the trunk?
Thanks,
Yufeng
include/opcode/
2013-02-26 Yufeng Zhang <yufeng.zhang@arm.com>
* aarch64.h (AARCH64_FEATURE_CRC): New macro.
opcodes/
2013-02-26 Yufeng Zhang <yufeng.zhang@arm.com>
* aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
(aarch64_feature_crc): New static.
(CRC): New macro.
(aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
* aarch64-asm-2.c: Re-generate.
* aarch64-dis-2.c: Ditto.
* aarch64-opc-2.c: Ditto.
gas/
2013-02-26 Yufeng Zhang <yufeng.zhang@arm.com>
* config/tc-aarch64.c (aarch64_features): Add the 'crc' option.
gas/testsuite/
2013-02-26 Yufeng Zhang <yufeng.zhang@arm.com>
* gas/aarch64/crc32.s: New test.
* gas/aarch64/crc32.d: Ditto.
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index ce59705..1a83b84 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -6987,6 +6987,7 @@ struct aarch64_option_cpu_value_table
};
static const struct aarch64_option_cpu_value_table aarch64_features[] = {
+ {"crc", AARCH64_FEATURE (AARCH64_FEATURE_CRC, 0)},
{"crypto", AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO, 0)},
{"fp", AARCH64_FEATURE (AARCH64_FEATURE_FP, 0)},
{"simd", AARCH64_FEATURE (AARCH64_FEATURE_SIMD, 0)},
diff --git a/gas/testsuite/gas/aarch64/crc32.d b/gas/testsuite/gas/aarch64/crc32.d
new file mode 100644
index 0000000..bba83b2
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/crc32.d
@@ -0,0 +1,16 @@
+#objdump: -dr
+#as: -march=armv8-a+crc
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0000000000000000 <.*>:
+ 0: 1acf40e3 crc32b w3, w7, w15
+ 4: 1ac345e7 crc32h w7, w15, w3
+ 8: 1ac7486f crc32w w15, w3, w7
+ c: 9acf4ce3 crc32x w3, w7, x15
+ 10: 1acf50e3 crc32cb w3, w7, w15
+ 14: 1ac355e7 crc32ch w7, w15, w3
+ 18: 1ac7586f crc32cw w15, w3, w7
+ 1c: 9acf5ce3 crc32cx w3, w7, x15
diff --git a/gas/testsuite/gas/aarch64/crc32.s b/gas/testsuite/gas/aarch64/crc32.s
new file mode 100644
index 0000000..34d9d92
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/crc32.s
@@ -0,0 +1,31 @@
+/* crc32.s Test file for AArch64 CRC-32 and CRC-32C checksum instructions.
+
+ Copyright 2013 Free Software Foundation, Inc.
+ Contributed by ARM Ltd.
+
+ This file is part of GAS.
+
+ GAS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the license, or
+ (at your option) any later version.
+
+ GAS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; see the file COPYING3. If not,
+ see <http://www.gnu.org/licenses/>. */
+
+
+ .text
+ crc32b w3, w7, w15
+ crc32h w7, w15, w3
+ crc32w w15, w3, w7
+ crc32x w3, w7, x15
+ crc32cb w3, w7, w15
+ crc32ch w7, w15, w3
+ crc32cw w15, w3, w7
+ crc32cx w3, w7, x15
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 941e678..eaf3cda 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -37,6 +37,7 @@ typedef uint32_t aarch64_insn;
#define AARCH64_FEATURE_CRYPTO 0x00010000 /* Crypto instructions. */
#define AARCH64_FEATURE_FP 0x00020000 /* FP instructions. */
#define AARCH64_FEATURE_SIMD 0x00040000 /* SIMD instructions. */
+#define AARCH64_FEATURE_CRC 0x00080000 /* CRC instructions. */
/* Architectures are the sum of the base and extensions. */
#define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 678ba78..2b1833b 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -163,12 +163,24 @@
QLF2(X,X), \
}
+/* e.g. CRC32B <Wd>, <Wn>, <Wm>. */
+#define QL_I3SAMEW \
+{ \
+ QLF3(W,W,W), \
+}
+
/* e.g. SMULH <Xd>, <Xn>, <Xm>. */
#define QL_I3SAMEX \
{ \
QLF3(X,X,X), \
}
+/* e.g. CRC32X <Wd>, <Wn>, <Xm>. */
+#define QL_I3WWX \
+{ \
+ QLF3(W,W,X), \
+}
+
/* e.g. UDIV <Xd>, <Xn>, <Xm>. */
#define QL_I3SAMER \
{ \
@@ -1199,11 +1211,14 @@ static const aarch64_feature_set aarch64_feature_simd =
AARCH64_FEATURE (AARCH64_FEATURE_SIMD, 0);
static const aarch64_feature_set aarch64_feature_crypto =
AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO, 0);
+static const aarch64_feature_set aarch64_feature_crc =
+ AARCH64_FEATURE (AARCH64_FEATURE_CRC, 0);
#define CORE &aarch64_feature_v8
#define FP &aarch64_feature_fp
#define SIMD &aarch64_feature_simd
#define CRYPTO &aarch64_feature_crypto
+#define CRC &aarch64_feature_crc
struct aarch64_opcode aarch64_opcode_table[] =
{
@@ -1810,6 +1825,15 @@ struct aarch64_opcode aarch64_opcode_table[] =
{"asr", 0x1ac02800, 0x7fe0fc00, dp_2src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_ALIAS},
{"rorv", 0x1ac02c00, 0x7fe0fc00, dp_2src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_HAS_ALIAS},
{"ror", 0x1ac02c00, 0x7fe0fc00, dp_2src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_ALIAS},
+ /* CRC instructions. */
+ {"crc32b", 0x1ac04000, 0xffe0fc00, dp_2src, 0, CRC, OP3 (Rd, Rn, Rm), QL_I3SAMEW, 0},
+ {"crc32h", 0x1ac04400, 0xffe0fc00, dp_2src, 0, CRC, OP3 (Rd, Rn, Rm), QL_I3SAMEW, 0},
+ {"crc32w", 0x1ac04800, 0xffe0fc00, dp_2src, 0, CRC, OP3 (Rd, Rn, Rm), QL_I3SAMEW, 0},
+ {"crc32x", 0x9ac04c00, 0xffe0fc00, dp_2src, 0, CRC, OP3 (Rd, Rn, Rm), QL_I3WWX, 0},
+ {"crc32cb", 0x1ac05000, 0xffe0fc00, dp_2src, 0, CRC, OP3 (Rd, Rn, Rm), QL_I3SAMEW, 0},
+ {"crc32ch", 0x1ac05400, 0xffe0fc00, dp_2src, 0, CRC, OP3 (Rd, Rn, Rm), QL_I3SAMEW, 0},
+ {"crc32cw", 0x1ac05800, 0xffe0fc00, dp_2src, 0, CRC, OP3 (Rd, Rn, Rm), QL_I3SAMEW, 0},
+ {"crc32cx", 0x9ac05c00, 0xffe0fc00, dp_2src, 0, CRC, OP3 (Rd, Rn, Rm), QL_I3WWX, 0},
/* Data-processing (3 source). */
{"madd", 0x1b000000, 0x7fe08000, dp_3src, 0, CORE, OP4 (Rd, Rn, Rm, Ra), QL_I4SAMER, F_HAS_ALIAS | F_SF},
{"mul", 0x1b007c00, 0x7fe0fc00, dp_3src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_ALIAS | F_SF},