On Tue, Dec 18, 2012 at 5:38 PM, Richard Earnshaw <firstname.lastname@example.org> wrote:
On 18/12/12 17:19, David Fernandez wrote:
On Tue, Dec 18, 2012 at 4:08 PM, Richard Earnshaw <email@example.com>
On 18/12/12 15:30, David Fernandez wrote:
Great, thanks for the info. That will keep me going. I'll look into
.inst, as I was using just a .word to define it for now.
Just as a comment to the whole thing, AFAIK both Cortex-Rn and
Cortex-An have in essence the same architecture, i.e. same instruction
set, same possible extensions, etc. The difference is that while
extensions like virt and sec are standard in Cortex-An, they are
optional in Cortex-Rn.
So I would suggest, that both armv7-r and arm-v7a should have access
to the same extensions, just that armv7-r will have most disabled by
default, while armv7-a would have some enabled by default.
Also, the banked registers instructions are not part of any extension,
and should be present all time. It is a bit weird that you don't have
them unless you enable the virt extension.
I'm not sure I understand what else you think is missing.
srsia sp!, #4
assembles without error for me.
Perhaps you can provide a test-case.
mrs r0, sp_usr
Complains, saying that this architecture does not support banked
I have to use .arch armv7-a and .arch_extension virt to make it work,
but it should work in armv7-r and without the need for virtualization
I'll look into it. However, Rev C of the v7 ARM ARM is quite explicit in
saying that this instruction is only available with the virtualization
extension, so on that basis, I think GAS is right. Do you have some
document that appears to contradict this?
I've read the architecture RevC, and the only reason that I can see
for you to say that is that any banked register tied to hypervisor or
monitor modes won't be available without those modes, which require
virtualization extensions for hypervisor (i.e. sp_hyp, spsr_hyp, or
elr_hyp), and security extensions for monitor mode (i.e.
sp_mon,spsr_mon). So depending on the architecture, and the extensions
enabled, gas might fail some of those instructions depending on the
But the banked registers for the normal processor modes like
supervisor, abort, undef, irq, and fiq, have to be there, as those
modes are present in all arm processors since arm7tdmi, and the
sections B9.3.11 & 12, does not indicate that virtualization
extensions are required, as it does for instructions like SMC (to
enter monitor mode through exception), which in section B9.3.14 says
"Security Extensions" on top of each encoding, or for HVC, which have
the virtualization extensions conditions in the instruction
May be I'm missing something, but the even the technical reference
manual shows that the normal banked register and modes are there, like
sp_svc, or lr_irq, ro_usr, etc.