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Re: [PATCH ARM]: Architectural Extensions (Matthew Gretton-Dann or Richard Earnshaw)

On 18/12/12 18:29, David Fernandez wrote:
On Tue, Dec 18, 2012 at 5:38 PM, Richard Earnshaw <> wrote:
On 18/12/12 17:19, David Fernandez wrote:

On Tue, Dec 18, 2012 at 4:08 PM, Richard Earnshaw <> wrote:

On 18/12/12 15:30, David Fernandez wrote:

Hi Richard,

Great, thanks for the info. That will keep me going. I'll look into
.inst, as I was using just a .word to define it for now.

Just as a comment to the whole thing, AFAIK both Cortex-Rn and
Cortex-An have in essence the same architecture, i.e. same instruction
set, same possible extensions, etc. The difference is that while
extensions like virt and sec are standard in Cortex-An, they are
optional in Cortex-Rn.

So I would suggest, that both armv7-r and arm-v7a should have access
to the same extensions, just that armv7-r will have most disabled by
default, while armv7-a would have some enabled by default.

Also, the banked registers instructions are not part of any extension,
and should be present all time. It is a bit weird that you don't have
them unless you enable the virt extension.

I'm not sure I understand what else you think is missing.

The file

          .arch armv7-r
          .syntax unified
          srsia   sp!, #4
          rfefd   sp!

assembles without error for me.

Perhaps you can provide a test-case.


Something like:

                  .arch   armv7-r
                  .syntax unified
                  mrs     r0, sp_usr
                  bx      lr

Complains, saying that this architecture does not support banked

I have to use .arch armv7-a and .arch_extension virt to make it work,
but it should work in armv7-r and without the need for virtualization


I'll look into it. However, Rev C of the v7 ARM ARM is quite explicit in saying that this instruction is only available with the virtualization extension, so on that basis, I think GAS is right. Do you have some document that appears to contradict this?


I've read the architecture RevC, and the only reason that I can see for you to say that is that any banked register tied to hypervisor or monitor modes won't be available without those modes, which require virtualization extensions for hypervisor (i.e. sp_hyp, spsr_hyp, or elr_hyp), and security extensions for monitor mode (i.e. sp_mon,spsr_mon). So depending on the architecture, and the extensions enabled, gas might fail some of those instructions depending on the arguments.

But the banked registers for the normal processor modes like
supervisor, abort, undef, irq, and fiq, have to be there, as those
modes are present in all arm processors since arm7tdmi, and the
sections B9.3.11 & 12, does not indicate that virtualization
extensions are required, as it does for instructions like SMC (to
enter monitor mode through exception), which in section B9.3.14 says
"Security Extensions" on top of each encoding, or for HVC, which have
the virtualization extensions conditions in the instruction

May be I'm missing something, but the even the technical reference
manual shows that the normal banked register and modes are there, like
sp_svc, or lr_irq, ro_usr, etc.


Ah, I think I see where you're coming from now...

Yes, banked registers exist in both the R and A profiles and have done since the very first ARM devices. However, that still doesn't mean that these instructions exist unless you have the virtualization extension. Instead, on cores that don't have the extension you have to jump through a few hoops to get at the banked registers. Essentially, to read registers in mode X, you have to (in pseudo-code):

	Switch_to_mode (X)
	Load/Save_banked_regs ()
	Switch_back_to_original_mode ()

The only exception to this is when X is user mode and you're in a system mode (since the final step would not be possible). In this case, there are variants of the LDM and STM that can access the user-mode registers directly and save them to a memory location. You can then access those values from memory.

A standard book on ARM system programming will probably explain this in much better detail than I can in a quick email, and probably provide most of the code you need as well.



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