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[Patch, microblaze, gas, opcodes] Add load/store byte reverse insns
- From: David Holsgrove <david dot holsgrove at xilinx dot com>
- To: "binutils at sourceware dot org" <binutils at sourceware dot org>
- Cc: John Williams <jwilliams at xilinx dot com>, Michael Eager <eager at eagerm dot com>, Vinod Kathail <vinodk at xilinx dot com>, Tom Shui <tshui at xilinx dot com>, Vidhumouli Hunsigida <vidhum at xilinx dot com>, Nagaraju Mekala <nmekala at xilinx dot com>, "Edgar E. Iglesias" <edgar dot iglesias at gmail dot com>
- Date: Thu, 8 Nov 2012 12:26:12 +0000
- Subject: [Patch, microblaze, gas, opcodes] Add load/store byte reverse insns
Add the endian reversing versions of load/store instructions;
lbur: Load byte unsigned, endian reversed
lhur: Load halfword unsigned, endian reversed
lwr: Load word, endian reversed
sbr: Store byte, endian reversed
shr: Store halfword, endian reversed
swr: Store word, endian reversed
binutils/opcodes/Changelog
2012-11-08 Edgar E. Iglesias <edgar.iglesias@gmail.com>
* microblaze-opc.h: Increase MAX_OPCODES
(op_code_struct): add lbur, lhur, lwr, sbr, shr, swr
* microblaze-opcm.h (microblaze_instr): add lbur,
lhur, lwr, sbr, shr, swr
binutils/gas/testsuite/Changelog
2012-11-08 David Holsgrove <david.holsgrove@xilinx.com>
* gas/microblaze/allinsn.exp: New file - test
newly added opcodes
* gas/microblaze/allinsn.s: Likewise
* gas/microblaze/allinsn.d: Likewise
From a64f11e3c57cd30bbda58906671f6706206131c9 Mon Sep 17 00:00:00 2001
From: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Date: Wed, 19 Oct 2011 21:12:29 +0200
Subject: [PATCH] opcodes/ * microblaze-opc.h: Add load/store byte reverse insns
Add the endian reversing versions of load/store instructions;
lbur: Load byte unsigned, endian reversed
lhur: Load halfword unsigned, endian reversed
lwr: Load word, endian reversed
sbr: Store byte, endian reversed
shr: Store halfword, endian reversed
swr: Store word, endian reversed
Include gas/testsuite/gas/microblaze/allinsn to test new insns
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
---
gas/testsuite/gas/microblaze/allinsn.d | 24 ++++++++++++++++++++++++
gas/testsuite/gas/microblaze/allinsn.exp | 5 +++++
gas/testsuite/gas/microblaze/allinsn.s | 27 +++++++++++++++++++++++++++
opcodes/microblaze-opc.h | 8 +++++++-
opcodes/microblaze-opcm.h | 2 +-
5 files changed, 64 insertions(+), 2 deletions(-)
create mode 100644 gas/testsuite/gas/microblaze/allinsn.d
create mode 100644 gas/testsuite/gas/microblaze/allinsn.exp
create mode 100644 gas/testsuite/gas/microblaze/allinsn.s
diff --git a/gas/testsuite/gas/microblaze/allinsn.d b/gas/testsuite/gas/microblaze/allinsn.d
new file mode 100644
index 0000000..79064ba
--- /dev/null
+++ b/gas/testsuite/gas/microblaze/allinsn.d
@@ -0,0 +1,24 @@
+#as:
+#objdump: -d
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <lbur>:
+ 0: c0000200 lbur r0, r0, r0
+
+00000004 <lhur>:
+ 4: c4000200 lhur r0, r0, r0
+
+00000008 <lwr>:
+ 8: c8000200 lwr r0, r0, r0
+
+0000000c <sbr>:
+ c: d0000200 sbr r0, r0, r0
+
+00000010 <shr>:
+ 10: d4000200 shr r0, r0, r0
+
+00000014 <swr>:
+ 14: d8000200 swr r0, r0, r0
diff --git a/gas/testsuite/gas/microblaze/allinsn.exp b/gas/testsuite/gas/microblaze/allinsn.exp
new file mode 100644
index 0000000..d1b1dea
--- /dev/null
+++ b/gas/testsuite/gas/microblaze/allinsn.exp
@@ -0,0 +1,5 @@
+# MicroBlaze test for special register.
+
+if [istarget microblaze*-*-*] {
+ run_dump_test "allinsn"
+}
diff --git a/gas/testsuite/gas/microblaze/allinsn.s b/gas/testsuite/gas/microblaze/allinsn.s
new file mode 100644
index 0000000..8bb3ef5
--- /dev/null
+++ b/gas/testsuite/gas/microblaze/allinsn.s
@@ -0,0 +1,27 @@
+ .text
+footext:
+ .text
+ .global lbur
+lbur:
+ lbur r0,r0,r0
+ .text
+ .global lhur
+lhur:
+ lhur r0,r0,r0
+ .text
+ .global lwr
+lwr:
+ lwr r0,r0,r0
+ .text
+ .global sbr
+sbr:
+ sbr r0,r0,r0
+ .text
+ .global shr
+shr:
+ shr r0,r0,r0
+ .text
+ .global swr
+swr:
+ swr r0,r0,r0
+
diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
index 02ac83f..44c9d38 100644
--- a/opcodes/microblaze-opc.h
+++ b/opcodes/microblaze-opc.h
@@ -96,7 +96,7 @@
#define DELAY_SLOT 1
#define NO_DELAY_SLOT 0
-#define MAX_OPCODES 280
+#define MAX_OPCODES 284
struct op_code_struct
{
@@ -220,12 +220,18 @@ struct op_code_struct
{"bgei", INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBCA00000, OPCODE_MASK_H1, bgei, branch_inst },
{"bgeid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBEA00000, OPCODE_MASK_H1, bgeid, branch_inst },
{"lbu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC0000000, OPCODE_MASK_H4, lbu, memory_load_inst },
+ {"lbur", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC0000200, OPCODE_MASK_H4, lbur, memory_load_inst },
{"lhu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC4000000, OPCODE_MASK_H4, lhu, memory_load_inst },
+ {"lhur", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC4000200, OPCODE_MASK_H4, lhur, memory_load_inst },
{"lw", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000000, OPCODE_MASK_H4, lw, memory_load_inst },
+ {"lwr", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000200, OPCODE_MASK_H4, lwr, memory_load_inst },
{"lwx", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000400, OPCODE_MASK_H4, lwx, memory_load_inst },
{"sb", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD0000000, OPCODE_MASK_H4, sb, memory_store_inst },
+ {"sbr", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD0000200, OPCODE_MASK_H4, sbr, memory_store_inst },
{"sh", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD4000000, OPCODE_MASK_H4, sh, memory_store_inst },
+ {"shr", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD4000200, OPCODE_MASK_H4, shr, memory_store_inst },
{"sw", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000000, OPCODE_MASK_H4, sw, memory_store_inst },
+ {"swr", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000200, OPCODE_MASK_H4, swr, memory_store_inst },
{"swx", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000400, OPCODE_MASK_H4, swx, memory_store_inst },
{"lbui", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE0000000, OPCODE_MASK_H, lbui, memory_load_inst },
{"lhui", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE4000000, OPCODE_MASK_H, lhui, memory_load_inst },
diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h
index 10acacf..522d9a8 100644
--- a/opcodes/microblaze-opcm.h
+++ b/opcodes/microblaze-opcm.h
@@ -36,7 +36,7 @@ enum microblaze_instr
bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni,
imm, rtsd, rtid, rtbd, rted, bri, brid, brlid, brai, braid, bralid,
brki, beqi, beqid, bnei, bneid, blti, bltid, blei, bleid, bgti,
- bgtid, bgei, bgeid, lbu, lhu, lw, lwx, sb, sh, sw, swx, lbui, lhui, lwi,
+ bgtid, bgei, bgeid, lbu, lbur, lhu, lhur, lw, lwr, lwx, sb, sbr, sh, shr, sw, swr, swx, lbui, lhui, lwi,
sbi, shi, swi, msrset, msrclr, tuqula, fadd, frsub, fmul, fdiv,
fcmp_lt, fcmp_eq, fcmp_le, fcmp_gt, fcmp_ne, fcmp_ge, fcmp_un, flt,
fint, fsqrt,
--
1.7.0.4