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[PATCH v2 09/12] opcodes/ * config/tc-microblaze.c: Add support for mbar and sleep insns
- From: david dot holsgrove at xilinx dot com
- To: binutils at sourceware dot org
- Cc: eager at eagercon dot com, edgar dot iglesias at gmail dot com, joseph at codesourcery dot com, john dot williams at xilinx dot com, vidhumouli dot hunsigida at xilinx dot com, nagaraju dot mekala at xilinx dot com, David Holsgrove <david dot holsgrove at xilinx dot com>
- Date: Thu, 11 Oct 2012 17:17:11 +1000
- Subject: [PATCH v2 09/12] opcodes/ * config/tc-microblaze.c: Add support for mbar and sleep insns
- References: <cover.1349938301.git.david.holsgrove@xilinx.com>
- References: <cover.1349938301.git.david.holsgrove@xilinx.com>
From: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
This patch is based on a patch from Kishore <kkatna@xilinx.com>
to add mbar.
Added mnemonic sleep instruction for mbar 16
Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
---
gas/ChangeLog | 4 ++++
gas/config/tc-microblaze.c | 18 ++++++++++++++++++
opcodes/ChangeLog | 6 ++++++
opcodes/microblaze-dis.c | 16 ++++++++++++++++
opcodes/microblaze-opc.h | 16 +++++++++++++---
opcodes/microblaze-opcm.h | 6 +++++-
6 files changed, 62 insertions(+), 4 deletions(-)
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 73ec28a..b8ac685 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,7 @@
+2012-10-10 Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+
+ * config/tc-microblaze.c: Add support for mbar and sleep insns
+
2012-10-10 Edgar E. Iglesias <edgar.iglesias@gmail.com>
* tc-microblaze.c: Add microblaze little endian support
diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
index 27bb7af..7d84776 100644
--- a/gas/config/tc-microblaze.c
+++ b/gas/config/tc-microblaze.c
@@ -1604,6 +1604,24 @@ md_assemble (char * str)
output = frag_more (isize);
break;
+ case INST_TYPE_IMM5:
+ if (strcmp(op_end, ""))
+ op_end = parse_imm (op_end + 1, & exp, MIN_IMM5, MAX_IMM5);
+ else
+ as_fatal(_("Error in statement syntax"));
+ if (exp.X_op != O_constant) {
+ as_warn(_("Symbol used as immediate for mbar instruction"));
+ } else {
+ output = frag_more (isize);
+ immed = exp.X_add_number;
+ }
+ if (immed != (immed % 32)) {
+ as_warn(_("Immediate value for mbar > 32. using <value %% 32>"));
+ immed = immed % 32;
+ }
+ inst |= (immed << IMM_MBAR);
+ break;
+
default:
as_fatal (_("unimplemented opcode \"%s\""), name);
}
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 0f06683..5753664 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,9 @@
+2012-10-10 Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+
+ * microblaze-opc.h: Add support for mbar and sleep insns
+ * microblaze-opcm.h: Likewise
+ * microblaze-dis.c: Likewise
+
2012-10-10 David Holsgrove <david.holsgrove@xilinx.com>
* microblaze-opc.h: Add support for clz insn
diff --git a/opcodes/microblaze-dis.c b/opcodes/microblaze-dis.c
index 4874cc9..9025da9 100644
--- a/opcodes/microblaze-dis.c
+++ b/opcodes/microblaze-dis.c
@@ -65,6 +65,15 @@ get_field_imm5 (long instr)
}
static char *
+get_field_imm5_mbar (long instr)
+{
+ char tmpstr[25];
+
+ sprintf(tmpstr, "%d", (short)((instr & IMM5_MBAR_MASK) >> IMM_MBAR));
+ return(strdup(tmpstr));
+}
+
+static char *
get_field_rfsl (long instr)
{
char tmpstr[25];
@@ -374,6 +383,13 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
case INST_TYPE_RD_IMM15:
print_func (stream, "\t%s, %s", get_field_rd (inst), get_field_imm15 (inst));
break;
+ /* For mbar insn. */
+ case INST_TYPE_IMM5:
+ print_func (stream, "\t%s", get_field_imm5_mbar (inst));
+ break;
+ /* For mbar 16 or sleep insn. */
+ case INST_TYPE_NONE:
+ break;
/* For tuqula instruction */
case INST_TYPE_RD:
print_func (stream, "\t%s", get_field_rd (inst));
diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
index 18480f6..78e5fa5 100644
--- a/opcodes/microblaze-opc.h
+++ b/opcodes/microblaze-opc.h
@@ -56,6 +56,9 @@
/* New insn type for t*put. */
#define INST_TYPE_RFSL 19
+/* For mbar. */
+#define INST_TYPE_IMM5 20
+
#define INST_TYPE_NONE 25
@@ -76,8 +79,8 @@
#define OPCODE_MASK_H2 0xFC1F0000 /* High 6 and bits 20-16. */
#define OPCODE_MASK_H12 0xFFFF0000 /* High 16. */
#define OPCODE_MASK_H4 0xFC0007FF /* High 6 and low 11 bits. */
-#define OPCODE_MASK_H13S 0xFFE0EFF0 /* High 11 and 15:1 bits and last
- nibble of last byte for spr. */
+#define OPCODE_MASK_H13S 0xFFE0E7F0 /* High 11 16:18 21:27 bits, 19:20 bits
+ and last nibble of last byte for spr. */
#define OPCODE_MASK_H23S 0xFC1FC000 /* High 6, 20-16 and 15:1 bits and last
nibble of last byte for spr. */
#define OPCODE_MASK_H34 0xFC00FFFF /* High 6 and low 16 bits. */
@@ -92,11 +95,13 @@
/* New Mask for msrset, msrclr insns. */
#define OPCODE_MASK_H23N 0xFC1F8000 /* High 6 and bits 11 - 16. */
+/* Mask for mbar insn. */
+#define OPCODE_MASK_HN 0xFF020004 /* High 16 bits and bits 14, 29. */
#define DELAY_SLOT 1
#define NO_DELAY_SLOT 0
-#define MAX_OPCODES 285
+#define MAX_OPCODES 286
struct op_code_struct
{
@@ -168,6 +173,8 @@ struct op_code_struct
{"sext16",INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000061, OPCODE_MASK_H34, sext16, logical_inst },
{"wic", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000068, OPCODE_MASK_H34B, wic, special_inst },
{"wdc", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000064, OPCODE_MASK_H34B, wdc, special_inst },
+ {"mbar", INST_TYPE_IMM5, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8020004, OPCODE_MASK_HN, mbar, special_inst },
+ {"sleep", INST_TYPE_NONE, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBA020004, OPCODE_MASK_HN, invalid_inst, special_inst }, /* translates to mbar 16. */
{"wdc.clear", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000066, OPCODE_MASK_H34B, wdcclear, special_inst },
{"wdc.flush", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000074, OPCODE_MASK_H34B, wdcflush, special_inst },
{"mts", INST_TYPE_SPECIAL_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MTS, 0x9400C000, OPCODE_MASK_H13S, mts, special_inst },
@@ -412,5 +419,8 @@ char pvr_register_prefix[] = "rpvr";
#define MIN_IMM15 ((int) 0x0000)
#define MAX_IMM15 ((int) 0x7fff)
+#define MIN_IMM5 ((int) 0x00000000)
+#define MAX_IMM5 ((int) 0x0000001f)
+
#endif /* MICROBLAZE_OPC */
diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h
index 661d836..7b8d20b 100644
--- a/opcodes/microblaze-opcm.h
+++ b/opcodes/microblaze-opcm.h
@@ -31,7 +31,7 @@ enum microblaze_instr
idiv, idivu, bsll, bsra, bsrl, get, put, nget, nput, cget, cput,
ncget, ncput, muli, bslli, bsrai, bsrli, mului, or, and, xor,
andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16,
- wic, wdc, wdcclear, wdcflush, mts, mfs, br, brd,
+ wic, wdc, wdcclear, wdcflush, mts, mfs, mbar, br, brd,
brld, bra, brad, brald, microblaze_brk, beq, beqd, bne, bned, blt,
bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni,
imm, rtsd, rtid, rtbd, rted, bri, brid, brlid, brai, braid, bralid,
@@ -121,6 +121,7 @@ enum microblaze_instr_type
#define RA_LOW 16 /* Low bit for RA. */
#define RB_LOW 11 /* Low bit for RB. */
#define IMM_LOW 0 /* Low bit for immediate. */
+#define IMM_MBAR 21 /* low bit for mbar instruction. */
#define RD_MASK 0x03E00000
#define RA_MASK 0x001F0000
@@ -130,6 +131,9 @@ enum microblaze_instr_type
/* Imm mask for barrel shifts. */
#define IMM5_MASK 0x0000001F
+/* Imm mask for mbar. */
+#define IMM5_MBAR_MASK 0x03E00000
+
/* FSL imm mask for get, put instructions. */
#define RFSL_MASK 0x000000F
--
1.7.0.4