68hc11/12/xgate - different memory maps on two cores, linker address offset

[James Murray <jsm at jsm-net dot demon dot co dot uk>]

I'm just getting back into my Freescale s12x / xgate patches for
binutils again.

The CPU I'm targeting has a main "S12" CISC core and a second "XGATE"
RISC core. They share memory space, but the memory map for the XGATE is
different to the main S12 CPU.

So, a variable at address 0x2000 on the main CPU is visible at 0xe000 on
the XGATE.
Presently, I'm using this workaround on the XGATE.

.equ xg_offset, 0xc000 ; 0x2000 on s12x = 0xe000 on xgate
.equ coilsel_xg, coilsel+xg_offset

So then in the xgate.s assembly code I use the variable "coilsel_xg" and
on the S12 core I use coilsel.

This code links and functions fine, but it is a crude hack to .equ all
the shared variables in order to add the 0xc000 offset.

Is there any easy way to direct the linker to do this automatically,
but only for code from the XGATE core?

I could, no doubt, hardcode the offset into the linker when linking in
XGATE code. However I'm not sure if this offset is constant (now/future)
across all microcontrollers using the XGATE.

any thoughts on a more general cleaner approach?

regards

James Murray