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Re: [MIPS] Add saa and saad instructions for octeon
On Tue, 15 Nov 2011, Andrew Pinski wrote:
> And here is the new patch with the new -march=octeon+ . Note there is
> a hack in the testsuite mips.exp's run_dump_test_arch as the mips64r2
> sync test for Octeon+ should use the Octeon's .d file.
Why don't you use an octeonp@ override instead just like some other tests
do? You can trivially refer to an octeon@ dump; see some r3000@ files for
examples.
Also:
--- gas/config/tc-mips.c 14 Nov 2011 13:43:21 -0000 1.494
+++ gas/config/tc-mips.c 15 Nov 2011 22:18:01 -0000
@@ -9117,6 +9120,53 @@ macro (struct mips_cl_insn *ip)
}
break;
+ case M_SAA_AB:
+ s = "saa";
+ goto saa_saad;
+ case M_SAAD_AB:
+ s = "saad";
+
+ saa_saad:
+ /* The saa/saad instructions do not specify offset. When invoked with
+ address or symbol then load the address or value of symbol in a
+ register using the la macro into AT, and pass the register for
+ emitting saa/saad instruction. This will get expanded to
+
+ la AT, constant/label
+ saa/saad $treg,(AT) */
+ {
+ /* Accept zero-displacement. */
+ if (breg
+ && offset_expr.X_op == O_constant
+ && offset_expr.X_add_number == 0)
+ {
+ macro_build (NULL, s, "t,(s)", treg, breg);
+ break;
+ }
This separate call to macro_build can be removed if you assign breg to
tempreg and then...
+
+ used_at = 1;
+ tempreg = AT;
+ /* If the offset_expr is a constant and in the range,
+ then just emit the {,d}addi. */
+ if (breg
+ && offset_expr.X_op == O_constant
+ && offset_expr.X_add_number >= -0x8000
+ && offset_expr.X_add_number < 0x8000)
+ macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
+ tempreg, breg, BFD_RELOC_LO16);
+ else
+ {
+ load_address (tempreg, &offset_expr, &used_at);
+ if (breg)
+ macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
+ tempreg, tempreg, breg);
+ }
+
+ /* The address part is forwarded through the global offset_expr. */
+ macro_build (NULL, s, "t,(s)", treg, AT);
... use tempreg here, which would be consistent with the conditional code
above.
+ break;
+ }
+
/* New code added to support COPZ instructions.
This code builds table entries out of the macros in mip_opcodes.
R4000 uses interlocks to handle coproc delays.
However, there's actually lots of code duplication here -- can you see if
you can wire this into generic load/store handling code starting from the
ld_st label in this function? You'd have to define a knob like off0 as
the third alternative to off12/!off12, but otherwise the bits should work
as they are.
As a benefit you'd be able to get proper reloc op handling, so that e.g.
saa $3, %gp_rel(foo)($2)
works just as with any other load/store instructions despite the lack of
immediate offset support -- that'd expand to:
li $1, %gp_rel(foo)
saa $3, ($1)
@@ -11014,7 +11064,7 @@ mips_ip (char *str, struct mips_cl_insn
we must have a left paren. */
/* This is dependent on the next operand specifier
is a base register specification. */
- gas_assert (args[1] == 'b'
+ gas_assert (args[1] == 'b' || args[1] == 's'
|| (mips_opts.micromips
&& args[1] == 'm'
&& (args[2] == 'l' || args[2] == 'n'
Is it really needed? Both 'b' and 's' use the same bit positions in the
instruction word and the only difference between them is that 'b' is
handled by GAS as a base register (which it is for SAA/SAAD IIUC) while
's' is handled as an ALU source register. Why are you using a "t,(s)"
format rather than "t,(b)"?
--- gas/testsuite/gas/mips/mips.exp 14 Nov 2011 13:43:23 -0000 1.193
+++ gas/testsuite/gas/mips/mips.exp 15 Nov 2011 22:18:01 -0000
@@ -308,7 +308,13 @@ proc run_dump_test_arch { name arch } {
set format [expr { $elf ? "elf" : $ecoff ? "ecoff" : "aout" }]
set proparch [lindex [mips_arch_properties $arch 0] 0]
- foreach prefix [list ${proparch}@${format}@ ${proparch}@ ${format}@] {
+ set prefixes [list ${proparch}@${format}@ ${proparch}@ ]
+ if { [ string match "octeon*" $proparch ] && $proparch != "octeon" } {
+ lappend prefixes octeon@
+ lappend prefixes octeon@${format}@
+ }
+ lappend prefixes ${format}@
+ foreach prefix ${prefixes} {
set archname ${prefix}${name}
if { [file exists "$srcdir/$subdir/${archname}.d"] } {
set name $archname
As noted above, please avoid the hack and just use proper overrides.
--- include/opcode/mips.h 24 Oct 2011 14:21:41 -0000 1.80
+++ include/opcode/mips.h 15 Nov 2011 22:18:02 -0000
@@ -1065,6 +1069,8 @@ enum
M_S_DOB,
M_S_DAB,
M_S_S,
+ M_SAA_AB,
+ M_SAAD_AB,
M_SC_AB,
M_SC_OB,
M_SCD_AB,
Index: opcodes/mips-opc.c
===================================================================
RCS file: /cvs/src/src/opcodes/mips-opc.c,v
retrieving revision 1.88
diff -u -p -r1.88 mips-opc.c
--- opcodes/mips-opc.c 9 Aug 2011 15:20:03 -0000 1.88
+++ opcodes/mips-opc.c 15 Nov 2011 22:18:02 -0000
@@ -1247,6 +1248,10 @@ const struct mips_opcode mips_builtin_op
{"rzu.ob", "X,Q", 0x78000020, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX|SB1 },
{"rzu.ob", "D,k", 0x4bc00020, 0xffe0f83f, WR_D|RD_S|RD_T, 0, N54 },
{"rzu.qh", "X,Q", 0x78200020, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX },
+{"saa", "t,(s)", 0x70000018, 0xfc00ffff, SM|RD_t|RD_b, 0, IOCTP },
+{"saa", "t,A(b)", 0, (int) M_SAA_AB, INSN_MACRO, 0, IOCTP },
+{"saad", "t,(s)", 0x70000019, 0xfc00ffff, SM|RD_t|RD_b, 0, IOCTP },
+{"saad", "t,A(b)", 0, (int) M_SAAD_AB, INSN_MACRO, 0, IOCTP },
{"sb", "t,o(b)", 0xa0000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 },
{"sb", "t,A(b)", 0, (int) M_SB_AB, INSN_MACRO, 0, I1 },
{"sc", "t,o(b)", 0xe0000000, 0xfc000000, SM|RD_t|WR_t|RD_b, 0, I2 },
Then for the reloc ops to work you'd have to define macros to handle the
"t,o(b)" format here.
Just a few notes from a bystander -- please disregard if Richard
disagrees.
Maciej