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On Sat, Nov 20, 2010 at 10:13 AM, Maciej W. Rozycki <macro@linux-mips.org> wrote: > Hi Nick, > >> My apologies for approving Mingming's patch without checking through your >> objections first. > > ?No worry -- we all make mistakes from time to time and this one can be > fixed quite easily. :) > >> I think that the placement of the loongson_3a entry in the elfxx-mips.c and >> tc-mips.c is not really that important, so I am inclined to let the patch >> stand as it is. > > ?The sort order of these lists has been broken previously already. ?This > always brings up confusion. ?I'll post a separate change to clean them up. > >> But your objections to the include/opcodes/mips.h patch is >> valid: >> >> > > > ? ?#define INSN_LOONGSON_2F ? ? ? ? ?0x80000000 >> > > > ?+/* Loongson 3A. ?*/ >> > > > ?+#define INSN_LOONGSON_3A ? ? ? ? ?0x80000400 >> > > > ? ?/* RMI Xlr instruction */ >> > > > ? ?#define INSN_XLR ? ? ? ? ? ? ? ? ? ? ? 0x00000020 >> > >> > one bit per CPU type and you need to update INSN_CHIP_MASK accordingly. >> >> How about this fix to correct the problem: >> >> Index: include/opcode/mips.h >> =================================================================== >> RCS file: /cvs/src/src/include/opcode/mips.h,v >> retrieving revision 1.68 >> diff -u -3 -p -r1.68 mips.h >> --- include/opcode/mips.h ? ? ? 11 Nov 2010 10:23:38 -0000 ? ? ?1.68 >> +++ include/opcode/mips.h ? ? ? 19 Nov 2010 16:43:22 -0000 >> @@ -556,8 +556,6 @@ static const unsigned int mips_isa_table >> ?#define INSN_DSP ? ? ? ? ? ? ? ? ?0x00001000 >> ?#define INSN_DSP64 ? ? ? ? ? ? ? ?0x00002000 >> -/* 0x00004000 is unused. ?*/ >> - >> ?/* MIPS-3D ASE */ >> ?#define INSN_MIPS3D ? ? ? ? ? ? ? 0x00008000 >> >> @@ -595,7 +593,8 @@ static const unsigned int mips_isa_table >> ?/* ST Microelectronics Loongson 2F. ?*/ >> ?#define INSN_LOONGSON_2F ? ? ? ? ?0x80000000 >> ?/* Loongson 3A. ?*/ >> -#define INSN_LOONGSON_3A ? ? ? ? ?0x80000400 >> +#define INSN_LOONGSON_3A ? ? ? ? ?0x00004000 >> + >> ?/* RMI Xlr instruction */ >> ?#define INSN_XLR ? ? ? ? ? ? ? ? 0x00000020 >> >> >> Ie making use of the one unused bit in the mask. ?Of course this does mean >> that next time a new MIPS architecture is added, this whole problem is going >> to have to be revisited. > > ?Well, 0x00004000 has already been assigned to the ASE range > (INSN_ASE_MASK), so we'd have to deallocate it there to use it as a CPU > flag. > > ?What I actually have in mind is this: > > 2010-11-20 ?Maciej W. Rozycki ?<macro@linux-mips.org> > > ? ? ? ?include/opcode/ > ? ? ? ?* mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A. > ? ? ? ?(INSN_LOONGSON_3A): Clear bit 31. > > I have passed it though regression testing with the mips64-linux target > with no problems reported. > > ?It looks like we still have got a couple of available bits left in the > mask as indicated by (INSN_CHIP_MASK | INSN_ASE_MASK | INSN_ISA_MASK), so > no need to worry about running short of them for a (short) while yet. > But this list begs for tidying up as well. > > ?Maciej > > binutils-2.20.51-20100925-3a-fix.patch > Index: binutils-2.20.51/include/opcode/mips.h > =================================================================== > --- binutils-2.20.51.orig/include/opcode/mips.h > +++ binutils-2.20.51/include/opcode/mips.h > @@ -544,7 +544,7 @@ static const unsigned int mips_isa_table > ? { 0x0001, 0x0003, 0x0607, 0x1e0f, 0x3e1f, 0x0a23, 0x3e63, 0x3ebf, 0x3fff }; > > ?/* Masks used for Chip specific instructions. ?*/ > -#define INSN_CHIP_MASK ? ? ? ? ? 0xc3ff0820 > +#define INSN_CHIP_MASK ? ? ? ? ? 0xc3ff0c20 > > ?/* Cavium Networks Octeon instructions. ?*/ > ?#define INSN_OCTEON ? ? ? ? ? ? ?0x00000800 > @@ -595,7 +595,7 @@ static const unsigned int mips_isa_table > ?/* ST Microelectronics Loongson 2F. ?*/ > ?#define INSN_LOONGSON_2F ? ? ? ? ?0x80000000 > ?/* Loongson 3A. ?*/ > -#define INSN_LOONGSON_3A ? ? ? ? ?0x80000400 > +#define INSN_LOONGSON_3A ? ? ? ? ?0x00000400 > ?/* RMI Xlr instruction */ > ?#define INSN_XLR ? ? ? ? ? ? ? ? 0x00000020 > Apologies for placing the Loongosn3A entry in a wrong place. This patch fix the problem in elfxx-mips.c and tc-mips.c. Maciej's patch for mips.h is Ok to me, thanks :) Thanks, Mingming Sun 2010-11-23 Mingming Sun <mingm.sun@gmail.com> bfd/ * elfxx-mips.c (mips_set_isa_flags): Move bfd_mach_loongson_3a after bfd_mach_mips_sb1. gas/ * config/tc-mips.c (mips_cpu_info_table): Move loongson3a after sb1.
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