This is the mail archive of the
binutils@sourceware.org
mailing list for the binutils project.
Re: [PATCH] MIPS: microMIPS ASE support
- From: Nathan Froyd <froydnj at codesourcery dot com>
- To: "Maciej W. Rozycki" <macro at codesourcery dot com>
- Cc: Richard Sandiford <rdsandiford at googlemail dot com>, binutils at sourceware dot org, Chao-ying Fu <fu at mips dot com>, Rich Fuhler <rich at mips dot com>, David Lau <davidlau at mips dot com>, Kevin Mills <kevinm at mips dot com>, Ilie Garbacea <ilie at mips dot com>, Catherine Moore <clm at codesourcery dot com>, Nathan Sidwell <nathan at codesourcery dot com>, Joseph Myers <joseph at codesourcery dot com>
- Date: Mon, 26 Jul 2010 06:25:44 -0700
- Subject: Re: [PATCH] MIPS: microMIPS ASE support
- References: <alpine.DEB.1.10.1005181806590.4023@tp.orcam.me.uk> <87y6fa9u3t.fsf@firetop.home> <alpine.DEB.1.10.1007112325020.2824@tp.orcam.me.uk>
On Mon, Jul 26, 2010 at 11:55:20AM +0100, Maciej W. Rozycki wrote:
> > Did you actually test this with n64, say with a gcc bootstrap? Same
> > comment goes for elfn32-mips.c.
> >
> > Why only do the linker relaxation for elf32-mips.c (o32, o64 & EABI)?
> > Why not for n32 and n64 too?
>
> The answer to all the questions is negative. There is no 64-bit
> microMIPS hardware available at the moment. The best bet might be QEMU --
> NathanF, have you implemented any of the 64-bit instructions in QEMU?
I have implemented support for the 64-bit instructions in QEMU. I
haven't really tested whether the instruction translation works
correctly for those instructions. (It should; there's nothing unusual
about the codepaths the 64-bit instructions take vs. their 32-bit
counterparts...but you never know...)
-Nathan