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[PATCH bfin] Four pseudo instructions
- From: Jie Zhang <jie dot zhang at analog dot com>
- To: Binutils <binutils at sourceware dot org>
- Date: Fri, 4 Sep 2009 12:37:48 +0800
- Subject: [PATCH bfin] Four pseudo instructions
Those pseudo instructions are mainly for ADI internal use. This patch
adds support of HLT pseudo instruction. It also changes codings of other
three pseudo instructons: DBGA, DBGAH and DBGAL such that more registers
can be asserted.
Previous encoding:
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
| 1 | 1 | 1 | 1 | 0 | - | - | - | - | - |.dbgop.....|.regtest...|
|.expected......................................................|
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
dbgop
0: DBGA (Dregs_lo, uimm16);
1: DBGA (Dregs_hi, uimm16);
2: DBGAL (Dregs, uimm16);
3: DBGAH (Dregs, uimm16);
4-7: reserved.
This encoding only allows Dregs to be asserted. With this patch, the new
encoding is
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
| 1 | 1 | 1 | 1 | 0 | - | - | - | dbgop |.grp.......|.regtest...|
|.expected......................................................|
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
This new encoding adds register group, thus all registers can be encoded.
dbgop
0: DBGA (D/P/I/L/M/Bregs_lo, uimm16);
1: DBGA (D/P/I/L/M/Bregs_hi, uimm16);
2: DBGAL (allregs, uimm16);
3: DBGAH (allregs, uimm16);
Committed.
Jie
gas/
* config/bfin-parse.y (asm_1): Implement HLT instruction.
Fix comments for DBGA, DBGAH and DBGAL.
* config/tc-bfin.c (bfin_gen_pseudodbg_assert): Change according
to the new encoding of DBGA, DBGAH, and DBGAL.
include/
* opcode/bfin.h (PseudoDbg_Assert): Add bits_grp and mask_grp.
(PseudoDbg_Assert_grp_bits, PseudoDbg_Assert_grp_mask): Define.
(PseudoDbg_Assert_dbgop_bits, PseudoDbg_Assert_dbgop_mask,
PseudoDbg_Assert_dontcare_bits, PseudoDbg_Assert_dontcare_mask):
Adjust accordingly.
(init_PseudoDbg_Assert): Add PseudoDbg_Assert_grp_bits and
PseudoDbg_Assert_grp_mask.
opcodes/
* bfin-dis.c (decode_pseudodbg_assert_0): Change according
to the new encoding of DBGA, DBGAH, and DBGAL.
(_print_insn_bfin): Likewise.
Index: gas/config/bfin-parse.y
===================================================================
RCS file: /cvs/src/src/gas/config/bfin-parse.y,v
retrieving revision 1.33
diff -u -p -r1.33 bfin-parse.y
--- gas/config/bfin-parse.y 3 Sep 2009 17:42:52 -0000 1.33
+++ gas/config/bfin-parse.y 4 Sep 2009 04:23:09 -0000
@@ -3588,21 +3588,27 @@ asm_1:
$$ = bfin_gen_pseudodbg (3, 5, 0);
}
+ | HLT
+ {
+ notethat ("psedoDEBUG: HLT\n");
+ $$ = bfin_gen_pseudodbg (3, 4, 0);
+ }
+
| DBGA LPAREN HALF_REG COMMA expr RPAREN
{
- notethat ("pseudodbg_assert: DBGA (dregs_lo , uimm16 )\n");
+ notethat ("pseudodbg_assert: DBGA (regs_lo/hi , uimm16 )\n");
$$ = bfin_gen_pseudodbg_assert (IS_H ($3), &$3, uimm16 ($5));
}
-
+
| DBGAH LPAREN REG COMMA expr RPAREN
{
- notethat ("pseudodbg_assert: DBGAH (dregs , uimm16 )\n");
+ notethat ("pseudodbg_assert: DBGAH (regs , uimm16 )\n");
$$ = bfin_gen_pseudodbg_assert (3, &$3, uimm16 ($5));
}
| DBGAL LPAREN REG COMMA expr RPAREN
{
- notethat ("psedodbg_assert: DBGAL (dregs , uimm16 )\n");
+ notethat ("psedodbg_assert: DBGAL (regs , uimm16 )\n");
$$ = bfin_gen_pseudodbg_assert (2, &$3, uimm16 ($5));
}
Index: gas/config/tc-bfin.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-bfin.c,v
retrieving revision 1.30
diff -u -p -r1.30 tc-bfin.c
--- gas/config/tc-bfin.c 3 Sep 2009 18:03:38 -0000 1.30
+++ gas/config/tc-bfin.c 4 Sep 2009 04:23:09 -0000
@@ -1791,10 +1791,13 @@ bfin_gen_pseudodbg (int fn, int reg, int
INSTR_T
bfin_gen_pseudodbg_assert (int dbgop, REG_T regtest, int expected)
{
+ int grp;
INIT (PseudoDbg_Assert);
ASSIGN (dbgop);
ASSIGN_R (regtest);
+ grp = GROUP (regtest);
+ ASSIGN (grp);
ASSIGN (expected);
return GEN_OPCODE32 ();
Index: include/opcode/bfin.h
===================================================================
RCS file: /cvs/src/src/include/opcode/bfin.h,v
retrieving revision 1.1
diff -u -p -r1.1 bfin.h
--- include/opcode/bfin.h 30 Sep 2005 15:12:52 -0000 1.1
+++ include/opcode/bfin.h 4 Sep 2009 04:23:10 -0000
@@ -939,7 +939,7 @@ typedef struct
/* PseudoDbg_assert
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
-| 1 | 1 | 1 | 1 | 0 | - | - | - | - | - |.dbgop.....|.regtest...|
+| 1 | 1 | 1 | 1 | 0 | - | - | - | dbgop |.grp.......|.regtest...|
|.expected......................................................|
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
*/
@@ -951,6 +951,8 @@ typedef struct
int mask_expected;
int bits_regtest;
int mask_regtest;
+ int bits_grp;
+ int mask_grp;
int bits_dbgop;
int mask_dbgop;
int bits_dontcare;
@@ -964,10 +966,12 @@ typedef struct
#define PseudoDbg_Assert_expected_mask 0xffff
#define PseudoDbg_Assert_regtest_bits 16
#define PseudoDbg_Assert_regtest_mask 0x7
-#define PseudoDbg_Assert_dbgop_bits 19
-#define PseudoDbg_Assert_dbgop_mask 0x7
-#define PseudoDbg_Assert_dontcare_bits 22
-#define PseudoDbg_Assert_dontcare_mask 0x1f
+#define PseudoDbg_Assert_grp_bits 19
+#define PseudoDbg_Assert_grp_mask 0x7
+#define PseudoDbg_Assert_dbgop_bits 22
+#define PseudoDbg_Assert_dbgop_mask 0x3
+#define PseudoDbg_Assert_dontcare_bits 24
+#define PseudoDbg_Assert_dontcare_mask 0x7
#define PseudoDbg_Assert_code_bits 27
#define PseudoDbg_Assert_code_mask 0x1f
@@ -976,6 +980,7 @@ typedef struct
PseudoDbg_Assert_opcode, \
PseudoDbg_Assert_expected_bits, PseudoDbg_Assert_expected_mask, \
PseudoDbg_Assert_regtest_bits, PseudoDbg_Assert_regtest_mask, \
+ PseudoDbg_Assert_grp_bits, PseudoDbg_Assert_grp_mask, \
PseudoDbg_Assert_dbgop_bits, PseudoDbg_Assert_dbgop_mask, \
PseudoDbg_Assert_dontcare_bits, PseudoDbg_Assert_dontcare_mask, \
PseudoDbg_Assert_code_bits, PseudoDbg_Assert_code_mask \
Index: opcodes/bfin-dis.c
===================================================================
RCS file: /cvs/src/src/opcodes/bfin-dis.c,v
retrieving revision 1.13
diff -u -p -r1.13 bfin-dis.c
--- opcodes/bfin-dis.c 3 Sep 2009 17:42:53 -0000 1.13
+++ opcodes/bfin-dis.c 4 Sep 2009 04:23:10 -0000
@@ -4574,17 +4574,18 @@ decode_pseudodbg_assert_0 (TIword iw0, T
{
/* pseudodbg_assert
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
- | 1 | 1 | 1 | 1 | 0 | - | - | - | - | - |.dbgop.....|.regtest...|
+ | 1 | 1 | 1 | 1 | 0 | - | - | - | dbgop |.grp.......|.regtest...|
|.expected......................................................|
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
int expected = ((iw1 >> PseudoDbg_Assert_expected_bits) & PseudoDbg_Assert_expected_mask);
int dbgop = ((iw0 >> (PseudoDbg_Assert_dbgop_bits - 16)) & PseudoDbg_Assert_dbgop_mask);
+ int grp = ((iw0 >> (PseudoDbg_Assert_grp_bits - 16)) & PseudoDbg_Assert_grp_mask);
int regtest = ((iw0 >> (PseudoDbg_Assert_regtest_bits - 16)) & PseudoDbg_Assert_regtest_mask);
if (dbgop == 0)
{
OUTS (outf, "DBGA (");
- OUTS (outf, dregs_lo (regtest));
+ OUTS (outf, regs_lo (regtest, grp));
OUTS (outf, ", ");
OUTS (outf, uimm16 (expected));
OUTS (outf, ")");
@@ -4592,7 +4593,7 @@ decode_pseudodbg_assert_0 (TIword iw0, T
else if (dbgop == 1)
{
OUTS (outf, "DBGA (");
- OUTS (outf, dregs_hi (regtest));
+ OUTS (outf, regs_hi (regtest, grp));
OUTS (outf, ", ");
OUTS (outf, uimm16 (expected));
OUTS (outf, ")");
@@ -4600,7 +4601,7 @@ decode_pseudodbg_assert_0 (TIword iw0, T
else if (dbgop == 2)
{
OUTS (outf, "DBGAL (");
- OUTS (outf, dregs (regtest));
+ OUTS (outf, allregs (regtest, grp));
OUTS (outf, ", ");
OUTS (outf, uimm16 (expected));
OUTS (outf, ")");
@@ -4608,7 +4609,7 @@ decode_pseudodbg_assert_0 (TIword iw0, T
else if (dbgop == 3)
{
OUTS (outf, "DBGAH (");
- OUTS (outf, dregs (regtest));
+ OUTS (outf, allregs (regtest, grp));
OUTS (outf, ", ");
OUTS (outf, uimm16 (expected));
OUTS (outf, ")");
@@ -4712,7 +4713,7 @@ _print_insn_bfin (bfd_vma pc, disassembl
else if ((iw0 & 0xFF00) == 0xF900)
rv = decode_pseudoOChar_0 (iw0, iw1, pc, outf);
#endif
- else if ((iw0 & 0xFFC0) == 0xf000 && (iw1 & 0x0000) == 0x0000)
+ else if ((iw0 & 0xFF00) == 0xf000 && (iw1 & 0x0000) == 0x0000)
rv = decode_pseudodbg_assert_0 (iw0, iw1, outf);
return rv;