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Re: MIPS PLT entry


On Fri, 12 Jun 2009, Fu, Chao-Ying wrote:

>   From elfxx-mips.c, we have
> 
> /* The format of subsequent PLT entries.  */
> static const bfd_vma mips_exec_plt_entry[] = {
>   0x3c0f0000,   /* lui $15, %hi(.got.plt entry)                 */
>   0x01f90000,   /* l[wd] $25, %lo(.got.plt entry)($15)          */
>   0x25f80000,   /* addiu $24, $15, %lo(.got.plt entry)          */
>   0x03200008    /* jr $25                                       */
> };
> 
>   Should we reorder the last two instructions to have jr and then addiu?

 There is a data dependency between the L[WD] instruction and the JR 
instruction and therefore for MIPS I processors you need an intermediate 
instruction to fill the load delay slot.  Of course if building for a 
higher processor (and in particular for LD, where it is guaranteed) you 
may swap the instructions, but it cannot be unconditional.

 It is worth noting there is no instruction to fill the jump delay slot of 
the JR instruction though -- the code works well for most of the PLT 
entries, because the LUI instruction of the subsequent entry is harmlessly 
executed there, but I'm concerned about the last stub -- having browsed 
the source I fail to see a place where provisions would be made to make 
sure the last entry to be safe and you cannot imply the first word of the 
following section will be safe to execute as the branch delay slot 
instruction here.  I'd expect something like an extra word with NOP to be 
placed at the end of .plt at the time the section is finished; I fear the 
alignment of the following section and the resulting zero-padding may be 
papering over the problem in many cases, but it is still there.

  Maciej


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