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Re: [PATCH] Update mtfsf and mtfsfi instructions to support new optional operands.

From: Peter Bergner <bergner at vnet dot ibm dot com>
To: Alan Modra <amodra at bigpond dot net dot au>
Cc: binutils at sourceware dot org, Segher Boessenkool <segher at kernel dot crashing dot org>
Date: Wed, 14 Jan 2009 16:07:55 -0600
Subject: Re: [PATCH] Update mtfsf and mtfsfi instructions to support new optional operands.
References: <20070515213441.GA4052@vervain.rchland.ibm.com> <e80a11b08fce3da1e15053808c88130f@kernel.crashing.org>

On Thu, 2007-05-17 at 14:57 +0200, Segher Boessenkool wrote:
> > -{ "mtfsfi",  XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } 
> > },
> > -{ "mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } 
> > },
> > +{ "mtfsfi",  XRC(63,134,0), XWRA_MASK|(3<<21)|(1<<11), COM, { BFF, U, 
> > W } },
> > +{ "mtfsfi.", XRC(63,134,1), XWRA_MASK|(3<<21)|(1<<11), COM, { BFF, U, 
> > W } },
> 
> > -{ "mtfsf",   XFL(63,711,0), XFL_MASK,	COM,		{ FLM, FRB } },
> > -{ "mtfsf.",  XFL(63,711,1), XFL_MASK,	COM,		{ FLM, FRB } },
> > +{ "mtfsf",   XFL(63,711,0), XFL_MASK,	COM,		{ FLM, FRB, XFL_L, XFL_W 
> > } },
> > +{ "mtfsf.",  XFL(63,711,1), XFL_MASK,	COM,		{ FLM, FRB, XFL_L, XFL_W 
> > } },
> 
> Shouldn't the new forms be marked POWER6-only, not COM?

Someone within IBM complained about an old binutils not supporting the
four operand form of mtfsf.  This made me look back at the code Alan
and I added for multiple optional operands.  I then came across Segher's
comment above, which Alan replied would be too hard given the code at the
time.  With my recent change to add a deprecated cpu_flags field, this is
now trivial...  However, adding the test cases for the insns exposed a
buglet where we weren't checking the deprecated field in the disassembler.

This has passed bootstrap and make check.  Ok for mainline?

Peter


opcodes/
	* ppc-dis.c (print_insn_powerpc): Skip insn if it is deprecated.
	* ppc-opc.c (powerpc_opcodes) <mtfsf, mtfsf.>: Deprecate the two
	operand form and enable the four operand form for POWER6 and later.
	<mtfsfi, mtfsfi.>: Deprecate the two operand form and enable the
	three operand form for POWER6 and later.

gas/testsuite/
	* gas/ppc/power6.s ("mtfsf", "mtfsf.", "mtfsfi", "mtfsfi."): Add tests.
	* gas/ppc/power6.d: Likewise.

Index: opcodes/ppc-dis.c
===================================================================
RCS file: /cvs/src/src/opcodes/ppc-dis.c,v
retrieving revision 1.36
diff -u -p -r1.36 ppc-dis.c
--- opcodes/ppc-dis.c	4 Dec 2008 10:29:16 -0000	1.36
+++ opcodes/ppc-dis.c	14 Jan 2009 21:45:38 -0000
@@ -266,7 +266,8 @@ print_insn_powerpc (bfd_vma memaddr,
 	continue;
 
       if ((insn & opcode->mask) != opcode->opcode
-	  || (opcode->flags & dialect) == 0)
+	  || (opcode->flags & dialect) == 0
+	  || (opcode->deprecated & dialect) != 0)
 	continue;
 
       /* Make two passes over the operands.  First see if any of them
Index: opcodes/ppc-opc.c
===================================================================
RCS file: /cvs/src/src/opcodes/ppc-opc.c,v
retrieving revision 1.113
diff -u -p -r1.113 ppc-opc.c
--- opcodes/ppc-opc.c	9 Jan 2009 18:50:58 -0000	1.113
+++ opcodes/ppc-opc.c	14 Jan 2009 21:45:39 -0000
@@ -4887,8 +4887,10 @@ const struct powerpc_opcode powerpc_opco
 
 {"dcmpoq",	X(63,130),	X_MASK,      POWER6,	PPCNONE,	{BF, FRA, FRB}},
 
-{"mtfsfi",  XRC(63,134,0), XWRA_MASK|(3<<21)|(1<<11), COM, PPCNONE,	{BFF, U, W}},
-{"mtfsfi.", XRC(63,134,1), XWRA_MASK|(3<<21)|(1<<11), COM, PPCNONE,	{BFF, U, W}},
+{"mtfsfi",  XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, POWER6,	{BFF, U}},
+{"mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, POWER6,	{BFF, U}},
+{"mtfsfi",  XRC(63,134,0), XWRA_MASK|(3<<21)|(1<<11), POWER6, PPCNONE,	{BFF, U, W}},
+{"mtfsfi.", XRC(63,134,1), XWRA_MASK|(3<<21)|(1<<11), POWER6, PPCNONE,	{BFF, U, W}},
 
 {"fnabs",	XRC(63,136,0),	XRA_MASK,    COM,	PPCNONE,	{FRT, FRB}},
 {"fnabs.",	XRC(63,136,1),	XRA_MASK,    COM,	PPCNONE,	{FRT, FRB}},
@@ -4937,8 +4939,10 @@ const struct powerpc_opcode powerpc_opco
 
 {"dtstsfq",	X(63,674),	X_MASK,      POWER6,	PPCNONE,	{BF, FRA, FRB}},
 
-{"mtfsf",	XFL(63,711,0),	XFL_MASK,    COM,	PPCNONE,	{FLM, FRB, XFL_L, W}},
-{"mtfsf.",	XFL(63,711,1),	XFL_MASK,    COM,	PPCNONE,	{FLM, FRB, XFL_L, W}},
+{"mtfsf",	XFL(63,711,0),	XFL_MASK,    COM,	POWER6,		{FLM, FRB}},
+{"mtfsf.",	XFL(63,711,1),	XFL_MASK,    COM,	POWER6,		{FLM, FRB}},
+{"mtfsf",	XFL(63,711,0),	XFL_MASK,    POWER6,	PPCNONE,	{FLM, FRB, XFL_L, W}},
+{"mtfsf.",	XFL(63,711,1),	XFL_MASK,    POWER6,	PPCNONE,	{FLM, FRB, XFL_L, W}},
 
 {"drdpq",	XRC(63,770,0),	X_MASK,      POWER6,	PPCNONE,	{FRT, FRB}},
 {"drdpq.",	XRC(63,770,1),	X_MASK,      POWER6,	PPCNONE,	{FRT, FRB}},
Index: gas/testsuite/gas/ppc/power6.s
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/ppc/power6.s,v
retrieving revision 1.2
diff -u -p -r1.2 power6.s
--- gas/testsuite/gas/ppc/power6.s	9 Sep 2008 13:25:05 -0000	1.2
+++ gas/testsuite/gas/ppc/power6.s	14 Jan 2009 21:45:38 -0000
@@ -47,3 +47,17 @@ start:
 	dcbz    1, 2
 	dcbzl   3, 4
 	dcbz    5, 6
+	mtfsf   6,10
+	mtfsf.  6,11
+	mtfsf   6,10,0,0
+	mtfsf.  6,11,0,0
+	mtfsf   6,10,0,1
+	mtfsf.  6,11,0,1
+	mtfsf   6,10,1,0
+	mtfsf.  6,11,1,0
+	mtfsfi  6,0
+	mtfsfi. 6,15
+	mtfsfi  6,0,0
+	mtfsfi. 6,15,0
+	mtfsfi  6,0,1
+	mtfsfi. 6,15,1
Index: gas/testsuite/gas/ppc/power6.d
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/ppc/power6.d,v
retrieving revision 1.2
diff -u -p -r1.2 power6.d
--- gas/testsuite/gas/ppc/power6.d	9 Sep 2008 13:25:05 -0000	1.2
+++ gas/testsuite/gas/ppc/power6.d	14 Jan 2009 21:45:38 -0000
@@ -52,3 +52,17 @@ Disassembly of section \.text:
   a8:	7c 01 17 ec 	dcbz    r1,r2
   ac:	7c 23 27 ec 	dcbzl   r3,r4
   b0:	7c 05 37 ec 	dcbz    r5,r6
+  b4:	fc 0c 55 8e 	mtfsf   6,f10
+  b8:	fc 0c 5d 8f 	mtfsf.  6,f11
+  bc:	fc 0c 55 8e 	mtfsf   6,f10
+  c0:	fc 0c 5d 8f 	mtfsf.  6,f11
+  c4:	fc 0d 55 8e 	mtfsf   6,f10,0,1
+  c8:	fc 0d 5d 8f 	mtfsf.  6,f11,0,1
+  cc:	fe 0c 55 8e 	mtfsf   6,f10,1,0
+  d0:	fe 0c 5d 8f 	mtfsf.  6,f11,1,0
+  d4:	ff 00 01 0c 	mtfsfi  6,0
+  d8:	ff 00 f1 0d 	mtfsfi. 6,15
+  dc:	ff 00 01 0c 	mtfsfi  6,0
+  e0:	ff 00 f1 0d 	mtfsfi. 6,15
+  e4:	ff 01 01 0c 	mtfsfi  6,0,1
+  e8:	ff 01 f1 0d 	mtfsfi. 6,15,1

Follow-Ups:
- Re: [PATCH] Update mtfsf and mtfsfi instructions to support new optional operands.
  - From: Alan Modra
- Re: [PATCH] Update mtfsf and mtfsfi instructions to support new optional operands.
  - From: Andreas Schwab

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