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Re: PACTH: Enable Intel AVX
On Mon, Apr 07, 2008 at 09:29:30AM +0100, Jan Beulich wrote:
> There's one oversight in the gas part: parse_real_register() shouldn't
> return ymm registers without the according feature(s) enabled.
Here is a patch to check it.
>
> Besides that I wonder whether AES and PCLMUL really imply MMX
> support? I don't think CPUID documentation allows any such
> implication.
>
AES/PCLMUL don't support MMX. But they do imply at least SSE2.
Thanks.
H.J.
----
gas/
2008-04-07 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (parse_real_register): Return AVX register
only if AVX is enabled.
gas/testsuite/
2008-04-07 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/att-regs.s: Add AVX register test.
* gas/i386/intel-regs.s: Likewise.
* gas/i386/att-regs.d: Updated.
* gas/i386/intel-regs.d: Likewise.
--- gas/config/tc-i386.c.foo 2008-04-05 06:49:00.000000000 -0700
+++ gas/config/tc-i386.c 2008-04-07 05:48:05.000000000 -0700
@@ -7685,6 +7685,9 @@ parse_real_register (char *reg_string, c
if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
return (const reg_entry *) NULL;
+ if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
+ return (const reg_entry *) NULL;
+
/* Don't allow fake index register unless allow_index_reg isn't 0. */
if (!allow_index_reg
&& (r->reg_num == RegEiz || r->reg_num == RegRiz))
--- gas/testsuite/gas/i386/att-regs.d.foo 2008-02-18 00:44:38.000000000 -0800
+++ gas/testsuite/gas/i386/att-regs.d 2008-04-07 05:56:23.000000000 -0700
@@ -34,6 +34,7 @@ Disassembly of section \.text:
.*:[ ]+dd c0[ ]+ffree[ ]+%st(\(0\))?
.*:[ ]+0f ef c0[ ]+pxor[ ]+%mm0,%mm0
.*:[ ]+0f 57 c0[ ]+xorps[ ]+%xmm0,%xmm0
+.*:[ ]+c5 fc 57 c0[ ]+vxorps[ ]+%ymm0,%ymm0,%ymm0
.*:[ ]+44[ ]+inc %esp
.*:[ ]+88 c0[ ]+mov[ ]+%al,%al
.*:[ ]+66 44[ ]+inc[ ]+%sp
--- gas/testsuite/gas/i386/att-regs.s.foo 2008-02-18 00:44:38.000000000 -0800
+++ gas/testsuite/gas/i386/att-regs.s 2008-04-07 05:53:44.000000000 -0700
@@ -42,6 +42,9 @@
.arch .sse
xorps xmm0, xmm0
+ .arch .avx
+ vxorps ymm0, ymm0, ymm0
+
.arch generic64
.code64
mov r8b, axl
--- gas/testsuite/gas/i386/intel-regs.d.foo 2008-02-18 00:44:38.000000000 -0800
+++ gas/testsuite/gas/i386/intel-regs.d 2008-04-07 05:56:43.000000000 -0700
@@ -34,6 +34,7 @@ Disassembly of section \.text:
.*:[ ]+dd c0[ ]+ffree[ ]+%st(\(0\))?
.*:[ ]+0f ef c0[ ]+pxor[ ]+%mm0,%mm0
.*:[ ]+0f 57 c0[ ]+xorps[ ]+%xmm0,%xmm0
+.*:[ ]+c5 fc 57 c0[ ]+vxorps[ ]+%ymm0,%ymm0,%ymm0
.*:[ ]+44[ ]+inc %esp
.*:[ ]+88 c0[ ]+mov[ ]+%al,%al
.*:[ ]+66 44[ ]+inc[ ]+%sp
--- gas/testsuite/gas/i386/intel-regs.s.foo 2008-02-18 00:44:38.000000000 -0800
+++ gas/testsuite/gas/i386/intel-regs.s 2008-04-07 05:53:47.000000000 -0700
@@ -42,6 +42,9 @@
.arch .sse
xorps xmm0, xmm0
+ .arch .avx
+ vxorps ymm0, ymm0, ymm0
+
.arch generic64
.code64
mov axl, r8b