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[RFA] PowerPC ISA 2.04 support
- From: Edmar Wienskoski <edmar at freescale dot com>
- To: binutils at sourceware dot org
- Date: Wed, 27 Feb 2008 14:24:45 -0600
- Subject: [RFA] PowerPC ISA 2.04 support
Freescale would like to contribute this patch to binutils. It implements new instructions
that are available on Power ISA 2.04
Could some PowerPC maintainer review and commit the patch ?
Thanks,
Edmar
gas/ChangeLog
2008-02-06 Edmar Wienskoski <edmar@freescale.com>
* config/tc-ppc.c (parse_cpu): Handle "isa204".
(md_show_usage): Document -misa204.
gas/testsuite/ChangeLog
2008-02-06 Edmar Wienskoski <edmar@freescale.com>
* gas/ppc/isa204.s, gas/ppc/isa204.d: New test.
* gas/ppc/ppc.exp: Run the new test
include/opcode/ChangeLog
2008-02-06 Edmar Wienskoski <edmar@freescale.com>
* ppc.h: (PPC_OPCODE_ISA204): New.
opcodes/ChangeLog
2008-02-06 Edmar Wienskoski <edmar@freescale.com>
* ppc-dis.c (powerpc_dialect): Handle "isa204".
(print_ppc_disassembler_options): Document -Misa204.
* ppc-opc.c: (DUIS, DUI): New.
(XRT, XRTRA): Likewise.
(ISA204): Likewise.
(powerpc_opcodes): Add new Power ISA 2.04 instructions.
diff -urN binutils-2.18.50/gas/config/tc-ppc.c binutils-2.18.50-ISA204/gas/config/tc-ppc.c
--- binutils-2.18.50/gas/config/tc-ppc.c 2008-01-04 08:53:50.000000000 -0600
+++ binutils-2.18.50-ISA204/gas/config/tc-ppc.c 2008-02-08 14:48:40.000000000 -0600
@@ -932,6 +932,10 @@
| PPC_OPCODE_64 | PPC_OPCODE_POWER4
| PPC_OPCODE_CELL);
}
+ else if (strcmp (arg, "isa204") == 0)
+ {
+ ppc_cpu |= PPC_OPCODE_ISA204;
+ }
/* -mcom means assemble for the common intersection between Power
and PowerPC. At present, we just allow the union, rather
than the intersection. */
@@ -1129,6 +1133,7 @@
-mpower5 generate code for Power5 architecture\n\
-mpower6 generate code for Power6 architecture\n\
-mcell generate code for Cell Broadband Engine architecture\n\
+-misa204 generate code for Power architecture ISA 2.04\n\
-mcom generate code Power/PowerPC common instructions\n\
-many generate code for any architecture (PWR/PWRX/PPC)\n"));
fprintf (stream, _("\
diff -urN binutils-2.18.50/gas/testsuite/gas/ppc/isa204.d binutils-2.18.50-ISA204/gas/testsuite/gas/ppc/isa204.d
--- binutils-2.18.50/gas/testsuite/gas/ppc/isa204.d 1969-12-31 18:00:00.000000000 -0600
+++ binutils-2.18.50-ISA204/gas/testsuite/gas/ppc/isa204.d 2008-02-08 16:42:48.000000000 -0600
@@ -0,0 +1,31 @@
+#as: -mppc -misa204
+#objdump: -dr -Misa204
+#name: Power ISA 2.04 tests
+
+.*: +file format elf(32)?(64)?-powerpc.*
+
+Disassembly of section \.text:
+
+0+0000000 <start>:
+ 0: 4c 00 00 4e rfdi
+ 4: 4c 1f f9 8c dnh 0,1023
+ 8: 4f e0 01 8c dnh 31,0
+ c: 7c 22 18 be lbepx r1,r2,r3
+ 10: 7c 85 32 3e lhepx r4,r5,r6
+ 14: 7c e8 48 3e lwepx r7,r8,r9
+ 18: 7d 4b 60 3a maskg r11,r10,r12
+ 1c: 7d ae 7c be lfdepx r13,r14,r15
+ 20: 7e 11 91 be stbepx r16,r17,r18
+ 24: 7e 74 ab 3e sthepx r19,r20,r21
+ 28: 7e d7 c1 3e stwepx r22,r23,r24
+ 2c: 7f 3a d9 3a stdepx r25,r26,r27
+ 30: 7f 9d f5 be stfdepx r28,r29,r30
+ 34: 7c 1f 00 7e dcbstep r31,r0
+ 38: 7c 01 10 fe dcbfep r1,r2
+ 3c: 7c 64 29 fe dcbtstep r3,r4,r5
+ 40: 7c c7 42 7e dcbtep r6,r7,r8
+ 44: 7c 09 57 be icbiep r9,r10
+ 48: 7c 0b 67 fe dcbzep r11,r12
+ 4c: 7c 00 69 dc msgclr r13
+ 50: 7c 00 71 9c msgsnd r14
+ 54: 7c 00 00 7c wait
diff -urN binutils-2.18.50/gas/testsuite/gas/ppc/isa204.s binutils-2.18.50-ISA204/gas/testsuite/gas/ppc/isa204.s
--- binutils-2.18.50/gas/testsuite/gas/ppc/isa204.s 1969-12-31 18:00:00.000000000 -0600
+++ binutils-2.18.50-ISA204/gas/testsuite/gas/ppc/isa204.s 2008-02-08 16:01:28.000000000 -0600
@@ -0,0 +1,25 @@
+# Power ISA 2.04 tests
+ .section ".text"
+start:
+ rfdi
+ dnh 0, 1023
+ dnh 31, 0
+ lbepx 1, 2, 3
+ lhepx 4, 5, 6
+ lwepx 7, 8, 9
+ ldepx 10, 11, 12
+ lfdepx 13, 14, 15
+ stbepx 16, 17, 18
+ sthepx 19, 20, 21
+ stwepx 22, 23, 24
+ stdepx 25, 26, 27
+ stfdepx 28, 29, 30
+ dcbstep 31, 0
+ dcbfep 1, 2
+ dcbtstep 3, 4, 5
+ dcbtep 6, 7, 8
+ icbiep 9, 10
+ dcbzep 11, 12
+ msgclr 13
+ msgsnd 14
+ wait
diff -urN binutils-2.18.50/gas/testsuite/gas/ppc/ppc.exp binutils-2.18.50-ISA204/gas/testsuite/gas/ppc/ppc.exp
--- binutils-2.18.50/gas/testsuite/gas/ppc/ppc.exp 2008-01-04 08:53:50.000000000 -0600
+++ binutils-2.18.50-ISA204/gas/testsuite/gas/ppc/ppc.exp 2008-02-08 14:42:46.000000000 -0600
@@ -44,5 +44,6 @@
run_dump_test "e500"
run_list_test "range" "-a32"
run_dump_test "ppc750ps"
+ run_dump_test "isa204"
}
}
diff -urN binutils-2.18.50/include/opcode/ppc.h binutils-2.18.50-ISA204/include/opcode/ppc.h
--- binutils-2.18.50/include/opcode/ppc.h 2007-08-23 19:56:30.000000000 -0500
+++ binutils-2.18.50-ISA204/include/opcode/ppc.h 2008-02-07 11:19:40.000000000 -0600
@@ -149,6 +149,9 @@
/* Opcode is supported by CPUs with paired singles support. */
#define PPC_OPCODE_PPCPS 0x10000000
+/* Opcode is supported by Power ISA 2.04 */
+#define PPC_OPCODE_ISA204 0x20000000
+
/* A macro to extract the major opcode from an instruction. */
#define PPC_OP(i) (((i) >> 26) & 0x3f)
diff -urN binutils-2.18.50/opcodes/ppc-dis.c binutils-2.18.50-ISA204/opcodes/ppc-dis.c
--- binutils-2.18.50/opcodes/ppc-dis.c 2007-08-23 19:56:30.000000000 -0500
+++ binutils-2.18.50-ISA204/opcodes/ppc-dis.c 2008-02-08 14:50:38.000000000 -0600
@@ -90,6 +90,10 @@
dialect |= PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC;
if (info->disassembler_options
+ && strstr (info->disassembler_options, "isa204") != NULL)
+ dialect |= PPC_OPCODE_ISA204;
+
+ if (info->disassembler_options
&& strstr (info->disassembler_options, "any") != NULL)
dialect |= PPC_OPCODE_ANY;
@@ -372,6 +376,7 @@
fprintf (stream, " power4 Disassemble the Power4 instructions\n");
fprintf (stream, " power5 Disassemble the Power5 instructions\n");
fprintf (stream, " power6 Disassemble the Power6 instructions\n");
+ fprintf (stream, " isa204 Disassemble the Power ISA 2.04 instructions\n");
fprintf (stream, " 32 Do not disassemble 64-bit instructions\n");
fprintf (stream, " 64 Allow disassembly of 64-bit instructions\n");
}
diff -urN binutils-2.18.50/opcodes/ppc-opc.c binutils-2.18.50-ISA204/opcodes/ppc-opc.c
--- binutils-2.18.50/opcodes/ppc-opc.c 2008-01-29 02:24:43.000000000 -0600
+++ binutils-2.18.50-ISA204/opcodes/ppc-opc.c 2008-02-08 15:50:33.000000000 -0600
@@ -237,9 +237,13 @@
{ 0xfffc, 0, NULL, NULL,
PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
+ /* The DUIS field in a XFX form instruction, 10 bits unsigned imediate */
+#define DUIS DS + 1
+ { 0x3ff, 11, NULL, NULL, 0 },
+
/* The E field in a wrteei instruction. */
/* And the W bit in the pair singles instructions. */
-#define E DS + 1
+#define E DUIS + 1
#define PSW E
{ 0x1, 15, NULL, NULL, 0 },
@@ -468,6 +472,7 @@
/* The TO field in a D or X form instruction. */
#define TO TBR + 1
+#define DUI TO
#define TO_MASK (0x1f << 21)
{ 0x1f, 21, NULL, NULL, 0 },
@@ -1455,6 +1460,15 @@
/* An X form instruction with the L bit specified. */
#define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
+/* An X form instruction with RT fields specified */
+#define XRT(op, xop, rt) (X ((op), (xop)) \
+ | ((((unsigned long)(rt)) & 0x1f) << 21))
+
+/* An X form instruction with RT and RA fields specified */
+#define XRTRA(op, xop, rt, ra) (X ((op), (xop)) \
+ | ((((unsigned long)(rt)) & 0x1f) << 21) \
+ | ((((unsigned long)(ra)) & 0x1f) << 16))
+
/* The mask for an X form comparison instruction. */
#define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
@@ -1677,6 +1691,7 @@
#define PPCCHLK PPC_OPCODE_CACHELCK
#define PPCCHLK64 PPC_OPCODE_CACHELCK | PPC_OPCODE_BOOKE64
#define PPCRFMCI PPC_OPCODE_RFMCI
+#define ISA204 PPC_OPCODE_ISA204
/* The opcode table.
@@ -2882,6 +2897,8 @@
{ "rfi", XL(19,50), 0xffffffff, COM, { 0 } },
{ "rfci", XL(19,51), 0xffffffff, PPC403 | BOOKE, { 0 } },
+{ "rfdi", XL(19,39), 0xffffffff, ISA204, { 0 } },
+{ "dnh", X(19,198), X_MASK, ISA204, { DUI, DUIS } },
{ "rfsvc", XL(19,82), 0xffffffff, POWER, { 0 } },
@@ -3479,6 +3496,26 @@
{ "mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
{ "mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
+{ "lbepx", X(31, 95), X_MASK, ISA204, { RT, RA, RB } },
+{ "lhepx", X(31, 287), X_MASK, ISA204, { RT, RA, RB } },
+{ "lwepx", X(31, 31), X_MASK, ISA204, { RT, RA, RB } },
+{ "ldepx", X(31, 29), X_MASK, ISA204, { RT, RA, RB } },
+{ "lfdepx", X(31, 607), X_MASK, ISA204, { RT, RA, RB } },
+{ "stbepx", X(31, 223), X_MASK, ISA204, { RS, RA, RB } },
+{ "sthepx", X(31, 415), X_MASK, ISA204, { RS, RA, RB } },
+{ "stwepx", X(31, 159), X_MASK, ISA204, { RS, RA, RB } },
+{ "stdepx", X(31, 157), X_MASK, ISA204, { RS, RA, RB } },
+{ "stfdepx", X(31, 735), X_MASK, ISA204, { RS, RA, RB } },
+{ "dcbstep", XRT(31, 63, 0), XRT_MASK, ISA204, { RA, RB }},
+{ "dcbfep", XRT(31, 127, 0), XRT_MASK, ISA204, { RA, RB }},
+{ "dcbtstep",XRT(31, 255, 0), X_MASK, ISA204, { RT, RA, RB }},
+{ "dcbtep", XRT(31, 319, 0), X_MASK, ISA204, { RT, RA, RB }},
+{ "icbiep", XRT(31, 991, 0), XRT_MASK, ISA204, { RA, RB }},
+{ "dcbzep", XRT(31, 1023,0), XRT_MASK, ISA204, { RA, RB }},
+{ "msgclr", XRTRA(31,238,0,0), XRTRA_MASK, ISA204, { RB }},
+{ "msgsnd", XRTRA(31,206,0,0), XRTRA_MASK, ISA204, { RB }},
+{ "wait", X(31,62), 0xffffffff, ISA204, { 0 }},
+
{ "icblce", X(31,238), X_MASK, PPCCHLK64, { CT, RA, RB }},
{ "mtsrin", X(31,242), XRA_MASK, PPC32, { RS, RB } },
{ "mtsri", X(31,242), XRA_MASK, POWER32, { RS, RB } },