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Re: PATCH: PR 658: i386 assembler and disassembler can't handle SIB with INDEX==4
On Thu, Sep 20, 2007 at 06:52:20AM -0700, H.J. Lu wrote:
> On Thu, Sep 20, 2007 at 08:10:21AM +0100, Jan Beulich wrote:
> > >> It turns out that Intel assembler uses EIZ/RIZ as fake index
> > >> registers for this purpose. This patch adds a new directive,
> > >> .allow_index_reg, which will allow EIZ/RIZ as index registers.
> > >> Are there any comments?
> > >>
> > >> Thanks.
> > >>
> > >
> > >Here is the updated patch. It displays EIZ/RIZ only when there
> > >is an ambiguity. That is "BASE" and "BASE + EIZ/RIZ" have different
> > >opcodes.
> >
> > I think that on the assembler end, using %eiz is fine, but on the disassembler
> > side this pseudo register shouldn't be displayed unless absolutely needed (i.e.
> >
> > [ ]*12:[ ]+8d b4 26 00 00 00 00[ ]+lea[ ]+0x0\(%esi,%eiz,1\),%esi
> >
> > should be
> >
> > [ ]*12:[ ]+8d b4 26 00 00 00 00[ ]+lea[ ]+0x0\(%esi,,1\),%esi
> >
> > or
> >
> > [ ]*12:[ ]+8d b4 26 00 00 00 00[ ]+lea[ ]+0x0\(%esi,1\),%esi
> >
> > depending on what appears to make more sense. Perhaps even more reasonably
> > we could introduce a new option (or tie this to suffix_always), and by default
> > retain the old behavior. With the option enabled, you could then of course always
> > display the fake index.
> >
>
> The problem is they are either invalid or different:
>
> bash-3.2$ cat x.s
> lea 0x0(%esi,1),%esi
> bash-3.2$ /usr/bin/as -o x.o x.s --32
> bash-3.2$ objdump -dr x.o
>
> x.o: file format elf32-i386
>
> Disassembly of section .text:
>
> 00000000 <.text>:
> 0: 8d 36 lea (%esi),%esi
> bash-3.2$ cat y.s
> lea 0x0(%esi,,1),%esi
> bash-3.2$ /usr/bin/as -o y.o y.s --32
> y.s: Assembler messages:
> y.s:1: Error: expecting scale factor of 1, 2, 4, or 8: got `'
> bash-3.2$
>
I am checking in this patch. I added tests for Intel mode as
well as 64bit.
H.J.
----
gas/
2007-09-20 H.J. Lu <hongjiu.lu@intel.com>
PR 658
* config/tc-i386.c (SCALE1_WHEN_NO_INDEX): Removed.
(set_allow_index_reg): New.
(allow_index_reg): Likewise.
(md_pseudo_table): Add "allow_index_reg" and
"disallow_index_reg".
(build_modrm_byte): Set i.sib.index to NO_INDEX_REGISTER for
fake index registers.
(i386_scale): Updated.
(i386_index_check): Support fake index registers.
(parse_real_register): Return NULL on eiz/riz if fake index
registers aren't allowed.
gas/testsuite/
2007-09-20 H.J. Lu <hongjiu.lu@intel.com>
PR 658
* gas/i386/i386.exp: Run sib-intel, x86-64-sib and
x86-64-sib-intel.
* gas/i386/nops-1-i386-i686.d: Updated.
* gas/i386/nops-1-i386.d: Likewise.
* gas/i386/nops-1.d: Likewise.
* gas/i386/nops-2-i386.d: Likewise.
* gas/i386/nops-2-merom.d: Likewise.
* gas/i386/nops-2.d: Likewise.
* gas/i386/nops-3-i386.d: Likewise.
* gas/i386/nops-3.d : Likewise.
* gas/i386/sib.d: Likewise.
* gas/i386/sib.s: Use %eiz in testcases.
* gas/i386/sib-intel.d: New.
* gas/i386/x86-64-sib-intel.d: Likewise.
* gas/i386/x86-64-sib.d: Likewise.
* gas/i386/x86-64-sib.s: Likewise.
ld/testsuite/
2007-09-20 H.J. Lu <hongjiu.lu@intel.com>
PR 658
* ld-i386/tlsbin.dd: Updated.
* ld-i386/tlsld1.dd: Likewise.
opcodes/
2007-09-20 H.J. Lu <hongjiu.lu@intel.com>
PR 658
* 386-dis.c (index64): New.
(index32): Likewise.
(intel_index64): Likewise.
(intel_index32): Likewise.
(att_index64): Likewise.
(att_index32): Likewise.
(print_insn): Set index64 and index32.
(OP_E_extended): Use index64/index32 for index register for
SIB with INDEX == 4.
* i386-opc.h (RegEiz): New.
(RegRiz): Likewise.
* i386-reg.tbl: Add eiz and riz.
* i386-tbl.h: Regenerated.
--- binutils/gas/config/tc-i386.c.fake 2007-09-19 10:01:40.000000000 -0700
+++ binutils/gas/config/tc-i386.c 2007-09-19 15:46:48.000000000 -0700
@@ -43,14 +43,6 @@
#define INFER_ADDR_PREFIX 1
#endif
-#ifndef SCALE1_WHEN_NO_INDEX
-/* Specifying a scale factor besides 1 when there is no index is
- futile. eg. `mov (%ebx,2),%al' does exactly the same as
- `mov (%ebx),%al'. To slavishly follow what the programmer
- specified, set SCALE1_WHEN_NO_INDEX to 0. */
-#define SCALE1_WHEN_NO_INDEX 1
-#endif
-
#ifndef DEFAULT_ARCH
#define DEFAULT_ARCH "i386"
#endif
@@ -66,6 +58,7 @@
static void set_code_flag (int);
static void set_16bit_gcc_code_flag (int);
static void set_intel_syntax (int);
+static void set_allow_index_reg (int);
static void set_cpu_arch (int);
#ifdef TE_PE
static void pe_directive_secrel (int);
@@ -294,6 +287,9 @@ static int intel_syntax = 0;
/* 1 if register prefix % not required. */
static int allow_naked_reg = 0;
+/* 1 if fake index register, eiz/riz, is allowed . */
+static int allow_index_reg = 0;
+
/* Register prefix used for error message. */
static const char *register_prefix = "%";
@@ -539,6 +535,8 @@ const pseudo_typeS md_pseudo_table[] =
{"code64", set_code_flag, CODE_64BIT},
{"intel_syntax", set_intel_syntax, 1},
{"att_syntax", set_intel_syntax, 0},
+ {"allow_index_reg", set_allow_index_reg, 1},
+ {"disallow_index_reg", set_allow_index_reg, 0},
#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
{"largecomm", handle_large_common, 0},
#else
@@ -1508,6 +1506,12 @@ set_intel_syntax (int syntax_flag)
}
static void
+set_allow_index_reg (int flag)
+{
+ allow_index_reg = flag;
+}
+
+static void
set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
{
SKIP_WHITESPACE ();
@@ -4517,7 +4521,11 @@ build_modrm_byte (void)
}
else /* !i.base_reg && i.index_reg */
{
- i.sib.index = i.index_reg->reg_num;
+ if (i.index_reg->reg_num == RegEiz
+ || i.index_reg->reg_num == RegRiz)
+ i.sib.index = NO_INDEX_REGISTER;
+ else
+ i.sib.index = i.index_reg->reg_num;
i.sib.base = NO_BASE_REGISTER;
i.sib.scale = i.log2_scale_factor;
i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
@@ -4625,16 +4633,14 @@ build_modrm_byte (void)
Any base register besides %esp will not use the
extra modrm byte. */
i.sib.index = NO_INDEX_REGISTER;
-#if !SCALE1_WHEN_NO_INDEX
- /* Another case where we force the second modrm
- byte. */
- if (i.log2_scale_factor)
- i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
-#endif
}
else
{
- i.sib.index = i.index_reg->reg_num;
+ if (i.index_reg->reg_num == RegEiz
+ || i.index_reg->reg_num == RegRiz)
+ i.sib.index = NO_INDEX_REGISTER;
+ else
+ i.sib.index = i.index_reg->reg_num;
i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
if ((i.index_reg->reg_flags & RegRex) != 0)
i.rex |= REX_X;
@@ -5740,9 +5746,7 @@ i386_scale (char *scale)
{
as_warn (_("scale factor of %d without an index register"),
1 << i.log2_scale_factor);
-#if SCALE1_WHEN_NO_INDEX
i.log2_scale_factor = 0;
-#endif
}
scale = input_line_pointer;
input_line_pointer = save;
@@ -5980,8 +5984,11 @@ i386_index_check (const char *operand_st
|| (i.index_reg
&& (!i.index_reg->reg_type.bitfield.baseindex
|| (i.prefix[ADDR_PREFIX] == 0
- && !i.index_reg->reg_type.bitfield.reg64)
+ && i.index_reg->reg_num != RegRiz
+ && !i.index_reg->reg_type.bitfield.reg64
+ )
|| (i.prefix[ADDR_PREFIX]
+ && i.index_reg->reg_num != RegEiz
&& !i.index_reg->reg_type.bitfield.reg32))))
ok = 0;
}
@@ -6008,7 +6015,8 @@ i386_index_check (const char *operand_st
if ((i.base_reg
&& !i.base_reg->reg_type.bitfield.reg32)
|| (i.index_reg
- && (!i.index_reg->reg_type.bitfield.reg32
+ && ((!i.index_reg->reg_type.bitfield.reg32
+ && i.index_reg->reg_num != RegEiz)
|| !i.index_reg->reg_type.bitfield.baseindex)))
ok = 0;
}
@@ -6904,6 +6912,12 @@ parse_real_register (char *reg_string, c
}
}
+ /* Don't allow fake index register unless allow_index_reg isn't 0. */
+ if (r != NULL
+ && !allow_index_reg
+ && (r->reg_num == RegEiz || r->reg_num == RegRiz))
+ return (const reg_entry *) NULL;
+
if (r != NULL
&& ((r->reg_flags & (RegRex64 | RegRex))
|| r->reg_type.bitfield.reg64)
--- binutils/gas/testsuite/gas/i386/i386.exp.fake 2007-09-14 12:23:44.000000000 -0700
+++ binutils/gas/testsuite/gas/i386/i386.exp 2007-09-20 09:11:38.000000000 -0700
@@ -46,6 +46,7 @@ if [expr ([istarget "i*86-*-*"] || [ist
run_dump_test "sub"
run_dump_test "prescott"
run_dump_test "sib"
+ run_dump_test "sib-intel"
run_dump_test "vmx"
run_dump_test "suffix"
run_dump_test "immed32"
@@ -196,6 +197,8 @@ if [expr ([istarget "i*86-*-*"] || [ista
run_dump_test "x86-64-mem-intel"
run_dump_test "x86-64-reg"
run_dump_test "x86-64-reg-intel"
+ run_dump_test "x86-64-sib"
+ run_dump_test "x86-64-sib-intel"
if { ![istarget "*-*-aix*"]
&& ![istarget "*-*-beos*"]
--- binutils/gas/testsuite/gas/i386/nops-1-i386-i686.d.fake 2007-07-23 13:03:23.000000000 -0700
+++ binutils/gas/testsuite/gas/i386/nops-1-i386-i686.d 2007-09-19 17:59:10.000000000 -0700
@@ -27,15 +27,15 @@ Disassembly of section .text:
0+10 <nop14>:
[ ]*10:[ ]+90[ ]+nop[ ]*
[ ]*11:[ ]+90[ ]+nop[ ]*
-[ ]*12:[ ]+8d b4 26 00 00 00 00[ ]+lea[ ]+0x0\(%esi\),%esi
-[ ]*19:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi\),%edi
+[ ]*12:[ ]+8d b4 26 00 00 00 00[ ]+lea[ ]+0x0\(%esi,%eiz,1\),%esi
+[ ]*19:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi,%eiz,1\),%edi
0+20 <nop13>:
[ ]*20:[ ]+90[ ]+nop[ ]*
[ ]*21:[ ]+90[ ]+nop[ ]*
[ ]*22:[ ]+90[ ]+nop[ ]*
[ ]*23:[ ]+8d b6 00 00 00 00[ ]+lea[ ]+0x0\(%esi\),%esi
-[ ]*29:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi\),%edi
+[ ]*29:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi,%eiz,1\),%edi
0+30 <nop12>:
[ ]*30:[ ]+90[ ]+nop[ ]*
@@ -51,8 +51,8 @@ Disassembly of section .text:
[ ]*42:[ ]+90[ ]+nop[ ]*
[ ]*43:[ ]+90[ ]+nop[ ]*
[ ]*44:[ ]+90[ ]+nop[ ]*
-[ ]*45:[ ]+8d 74 26 00[ ]+lea[ ]+0x0\(%esi\),%esi
-[ ]*49:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi\),%edi
+[ ]*45:[ ]+8d 74 26 00[ ]+lea[ ]+0x0\(%esi,%eiz,1\),%esi
+[ ]*49:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi,%eiz,1\),%edi
0+50 <nop10>:
[ ]*50:[ ]+90[ ]+nop[ ]*
@@ -62,7 +62,7 @@ Disassembly of section .text:
[ ]*54:[ ]+90[ ]+nop[ ]*
[ ]*55:[ ]+90[ ]+nop[ ]*
[ ]*56:[ ]+8d 76 00[ ]+lea[ ]+0x0\(%esi\),%esi
-[ ]*59:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi\),%edi
+[ ]*59:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi,%eiz,1\),%edi
0+60 <nop9>:
[ ]*60:[ ]+90[ ]+nop[ ]*
@@ -73,7 +73,7 @@ Disassembly of section .text:
[ ]*65:[ ]+90[ ]+nop[ ]*
[ ]*66:[ ]+90[ ]+nop[ ]*
[ ]*67:[ ]+89 f6[ ]+mov[ ]+%esi,%esi
-[ ]*69:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi\),%edi
+[ ]*69:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi,%eiz,1\),%edi
0+70 <nop8>:
[ ]*70:[ ]+90[ ]+nop[ ]*
@@ -85,7 +85,7 @@ Disassembly of section .text:
[ ]*76:[ ]+90[ ]+nop[ ]*
[ ]*77:[ ]+90[ ]+nop[ ]*
[ ]*78:[ ]+90[ ]+nop[ ]*
-[ ]*79:[ ]+8d b4 26 00 00 00 00[ ]+lea[ ]+0x0\(%esi\),%esi
+[ ]*79:[ ]+8d b4 26 00 00 00 00[ ]+lea[ ]+0x0\(%esi,%eiz,1\),%esi
0+80 <nop7>:
[ ]*80:[ ]+90[ ]+nop[ ]*
@@ -97,7 +97,7 @@ Disassembly of section .text:
[ ]*86:[ ]+90[ ]+nop[ ]*
[ ]*87:[ ]+90[ ]+nop[ ]*
[ ]*88:[ ]+90[ ]+nop[ ]*
-[ ]*89:[ ]+8d b4 26 00 00 00 00[ ]+lea[ ]+0x0\(%esi\),%esi
+[ ]*89:[ ]+8d b4 26 00 00 00 00[ ]+lea[ ]+0x0\(%esi,%eiz,1\),%esi
0+90 <nop6>:
[ ]*90:[ ]+90[ ]+nop[ ]*
@@ -125,7 +125,7 @@ Disassembly of section .text:
[ ]*a9:[ ]+90[ ]+nop[ ]*
[ ]*aa:[ ]+90[ ]+nop[ ]*
[ ]*ab:[ ]+90[ ]+nop[ ]*
-[ ]*ac:[ ]+8d 74 26 00[ ]+lea[ ]+0x0\(%esi\),%esi
+[ ]*ac:[ ]+8d 74 26 00[ ]+lea[ ]+0x0\(%esi,%eiz,1\),%esi
0+b0 <nop4>:
[ ]*b0:[ ]+90[ ]+nop[ ]*
@@ -140,7 +140,7 @@ Disassembly of section .text:
[ ]*b9:[ ]+90[ ]+nop[ ]*
[ ]*ba:[ ]+90[ ]+nop[ ]*
[ ]*bb:[ ]+90[ ]+nop[ ]*
-[ ]*bc:[ ]+8d 74 26 00[ ]+lea[ ]+0x0\(%esi\),%esi
+[ ]*bc:[ ]+8d 74 26 00[ ]+lea[ ]+0x0\(%esi,%eiz,1\),%esi
0+c0 <nop3>:
[ ]*c0:[ ]+90[ ]+nop[ ]*
--- binutils/gas/testsuite/gas/i386/nops-1-i386.d.fake 2007-07-24 15:03:59.000000000 -0700
+++ binutils/gas/testsuite/gas/i386/nops-1-i386.d 2007-09-19 17:59:10.000000000 -0700
@@ -27,15 +27,15 @@ Disassembly of section .text:
0+10 <nop14>:
[ ]*10:[ ]+90[ ]+nop[ ]*
[ ]*11:[ ]+90[ ]+nop[ ]*
-[ ]*12:[ ]+8d b4 26 00 00 00 00[ ]+lea[ ]+0x0\(%esi\),%esi
-[ ]*19:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi\),%edi
+[ ]*12:[ ]+8d b4 26 00 00 00 00[ ]+lea[ ]+0x0\(%esi,%eiz,1\),%esi
+[ ]*19:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi,%eiz,1\),%edi
0+20 <nop13>:
[ ]*20:[ ]+90[ ]+nop[ ]*
[ ]*21:[ ]+90[ ]+nop[ ]*
[ ]*22:[ ]+90[ ]+nop[ ]*
[ ]*23:[ ]+8d b6 00 00 00 00[ ]+lea[ ]+0x0\(%esi\),%esi
-[ ]*29:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi\),%edi
+[ ]*29:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi,%eiz,1\),%edi
0+30 <nop12>:
[ ]*30:[ ]+90[ ]+nop[ ]*
@@ -51,8 +51,8 @@ Disassembly of section .text:
[ ]*42:[ ]+90[ ]+nop[ ]*
[ ]*43:[ ]+90[ ]+nop[ ]*
[ ]*44:[ ]+90[ ]+nop[ ]*
-[ ]*45:[ ]+8d 74 26 00[ ]+lea[ ]+0x0\(%esi\),%esi
-[ ]*49:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi\),%edi
+[ ]*45:[ ]+8d 74 26 00[ ]+lea[ ]+0x0\(%esi,%eiz,1\),%esi
+[ ]*49:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi,%eiz,1\),%edi
0+50 <nop10>:
[ ]*50:[ ]+90[ ]+nop[ ]*
@@ -62,7 +62,7 @@ Disassembly of section .text:
[ ]*54:[ ]+90[ ]+nop[ ]*
[ ]*55:[ ]+90[ ]+nop[ ]*
[ ]*56:[ ]+8d 76 00[ ]+lea[ ]+0x0\(%esi\),%esi
-[ ]*59:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi\),%edi
+[ ]*59:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi,%eiz,1\),%edi
0+60 <nop9>:
[ ]*60:[ ]+90[ ]+nop[ ]*
@@ -73,7 +73,7 @@ Disassembly of section .text:
[ ]*65:[ ]+90[ ]+nop[ ]*
[ ]*66:[ ]+90[ ]+nop[ ]*
[ ]*67:[ ]+89 f6[ ]+mov[ ]+%esi,%esi
-[ ]*69:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi\),%edi
+[ ]*69:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi,%eiz,1\),%edi
0+70 <nop8>:
[ ]*70:[ ]+90[ ]+nop[ ]*
@@ -85,7 +85,7 @@ Disassembly of section .text:
[ ]*76:[ ]+90[ ]+nop[ ]*
[ ]*77:[ ]+90[ ]+nop[ ]*
[ ]*78:[ ]+90[ ]+nop[ ]*
-[ ]*79:[ ]+8d b4 26 00 00 00 00[ ]+lea[ ]+0x0\(%esi\),%esi
+[ ]*79:[ ]+8d b4 26 00 00 00 00[ ]+lea[ ]+0x0\(%esi,%eiz,1\),%esi
0+80 <nop7>:
[ ]*80:[ ]+90[ ]+nop[ ]*
@@ -97,7 +97,7 @@ Disassembly of section .text:
[ ]*86:[ ]+90[ ]+nop[ ]*
[ ]*87:[ ]+90[ ]+nop[ ]*
[ ]*88:[ ]+90[ ]+nop[ ]*
-[ ]*89:[ ]+8d b4 26 00 00 00 00[ ]+lea[ ]+0x0\(%esi\),%esi
+[ ]*89:[ ]+8d b4 26 00 00 00 00[ ]+lea[ ]+0x0\(%esi,%eiz,1\),%esi
0+90 <nop6>:
[ ]*90:[ ]+90[ ]+nop[ ]*
@@ -125,7 +125,7 @@ Disassembly of section .text:
[ ]*a9:[ ]+90[ ]+nop[ ]*
[ ]*aa:[ ]+90[ ]+nop[ ]*
[ ]*ab:[ ]+90[ ]+nop[ ]*
-[ ]*ac:[ ]+8d 74 26 00[ ]+lea[ ]+0x0\(%esi\),%esi
+[ ]*ac:[ ]+8d 74 26 00[ ]+lea[ ]+0x0\(%esi,%eiz,1\),%esi
0+b0 <nop4>:
[ ]*b0:[ ]+90[ ]+nop[ ]*
@@ -140,7 +140,7 @@ Disassembly of section .text:
[ ]*b9:[ ]+90[ ]+nop[ ]*
[ ]*ba:[ ]+90[ ]+nop[ ]*
[ ]*bb:[ ]+90[ ]+nop[ ]*
-[ ]*bc:[ ]+8d 74 26 00[ ]+lea[ ]+0x0\(%esi\),%esi
+[ ]*bc:[ ]+8d 74 26 00[ ]+lea[ ]+0x0\(%esi,%eiz,1\),%esi
0+c0 <nop3>:
[ ]*c0:[ ]+90[ ]+nop[ ]*
--- binutils/gas/testsuite/gas/i386/nops-1.d.fake 2006-06-23 14:47:36.000000000 -0700
+++ binutils/gas/testsuite/gas/i386/nops-1.d 2007-09-19 17:59:10.000000000 -0700
@@ -26,15 +26,15 @@ Disassembly of section .text:
0+10 <nop14>:
[ ]*10:[ ]+90[ ]+nop[ ]*
[ ]*11:[ ]+90[ ]+nop[ ]*
-[ ]*12:[ ]+8d b4 26 00 00 00 00[ ]+lea[ ]+0x0\(%esi\),%esi
-[ ]*19:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi\),%edi
+[ ]*12:[ ]+8d b4 26 00 00 00 00[ ]+lea[ ]+0x0\(%esi,%eiz,1\),%esi
+[ ]*19:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi,%eiz,1\),%edi
0+20 <nop13>:
[ ]*20:[ ]+90[ ]+nop[ ]*
[ ]*21:[ ]+90[ ]+nop[ ]*
[ ]*22:[ ]+90[ ]+nop[ ]*
[ ]*23:[ ]+8d b6 00 00 00 00[ ]+lea[ ]+0x0\(%esi\),%esi
-[ ]*29:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi\),%edi
+[ ]*29:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi,%eiz,1\),%edi
0+30 <nop12>:
[ ]*30:[ ]+90[ ]+nop[ ]*
@@ -50,8 +50,8 @@ Disassembly of section .text:
[ ]*42:[ ]+90[ ]+nop[ ]*
[ ]*43:[ ]+90[ ]+nop[ ]*
[ ]*44:[ ]+90[ ]+nop[ ]*
-[ ]*45:[ ]+8d 74 26 00[ ]+lea[ ]+0x0\(%esi\),%esi
-[ ]*49:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi\),%edi
+[ ]*45:[ ]+8d 74 26 00[ ]+lea[ ]+0x0\(%esi,%eiz,1\),%esi
+[ ]*49:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi,%eiz,1\),%edi
0+50 <nop10>:
[ ]*50:[ ]+90[ ]+nop[ ]*
@@ -61,7 +61,7 @@ Disassembly of section .text:
[ ]*54:[ ]+90[ ]+nop[ ]*
[ ]*55:[ ]+90[ ]+nop[ ]*
[ ]*56:[ ]+8d 76 00[ ]+lea[ ]+0x0\(%esi\),%esi
-[ ]*59:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi\),%edi
+[ ]*59:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi,%eiz,1\),%edi
0+60 <nop9>:
[ ]*60:[ ]+90[ ]+nop[ ]*
@@ -72,7 +72,7 @@ Disassembly of section .text:
[ ]*65:[ ]+90[ ]+nop[ ]*
[ ]*66:[ ]+90[ ]+nop[ ]*
[ ]*67:[ ]+89 f6[ ]+mov[ ]+%esi,%esi
-[ ]*69:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi\),%edi
+[ ]*69:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi,%eiz,1\),%edi
0+70 <nop8>:
[ ]*70:[ ]+90[ ]+nop[ ]*
@@ -84,7 +84,7 @@ Disassembly of section .text:
[ ]*76:[ ]+90[ ]+nop[ ]*
[ ]*77:[ ]+90[ ]+nop[ ]*
[ ]*78:[ ]+90[ ]+nop[ ]*
-[ ]*79:[ ]+8d b4 26 00 00 00 00[ ]+lea[ ]+0x0\(%esi\),%esi
+[ ]*79:[ ]+8d b4 26 00 00 00 00[ ]+lea[ ]+0x0\(%esi,%eiz,1\),%esi
0+80 <nop7>:
[ ]*80:[ ]+90[ ]+nop[ ]*
@@ -96,7 +96,7 @@ Disassembly of section .text:
[ ]*86:[ ]+90[ ]+nop[ ]*
[ ]*87:[ ]+90[ ]+nop[ ]*
[ ]*88:[ ]+90[ ]+nop[ ]*
-[ ]*89:[ ]+8d b4 26 00 00 00 00[ ]+lea[ ]+0x0\(%esi\),%esi
+[ ]*89:[ ]+8d b4 26 00 00 00 00[ ]+lea[ ]+0x0\(%esi,%eiz,1\),%esi
0+90 <nop6>:
[ ]*90:[ ]+90[ ]+nop[ ]*
@@ -124,7 +124,7 @@ Disassembly of section .text:
[ ]*a9:[ ]+90[ ]+nop[ ]*
[ ]*aa:[ ]+90[ ]+nop[ ]*
[ ]*ab:[ ]+90[ ]+nop[ ]*
-[ ]*ac:[ ]+8d 74 26 00[ ]+lea[ ]+0x0\(%esi\),%esi
+[ ]*ac:[ ]+8d 74 26 00[ ]+lea[ ]+0x0\(%esi,%eiz,1\),%esi
0+b0 <nop4>:
[ ]*b0:[ ]+90[ ]+nop[ ]*
@@ -139,7 +139,7 @@ Disassembly of section .text:
[ ]*b9:[ ]+90[ ]+nop[ ]*
[ ]*ba:[ ]+90[ ]+nop[ ]*
[ ]*bb:[ ]+90[ ]+nop[ ]*
-[ ]*bc:[ ]+8d 74 26 00[ ]+lea[ ]+0x0\(%esi\),%esi
+[ ]*bc:[ ]+8d 74 26 00[ ]+lea[ ]+0x0\(%esi,%eiz,1\),%esi
0+c0 <nop3>:
[ ]*c0:[ ]+90[ ]+nop[ ]*
--- binutils/gas/testsuite/gas/i386/nops-2-i386.d.fake 2007-07-24 15:03:59.000000000 -0700
+++ binutils/gas/testsuite/gas/i386/nops-2-i386.d 2007-09-19 17:59:10.000000000 -0700
@@ -10,7 +10,7 @@ Disassembly of section .text:
0+ <nop>:
[ ]*0:[ ]+0f 44 c0[ ]+cmove[ ]+%eax,%eax
[ ]*3:[ ]+8d b6 00 00 00 00[ ]+lea[ ]+0x0\(%esi\),%esi
-[ ]*9:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi\),%edi
+[ ]*9:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi,%eiz,1\),%edi
0+10 <nop15>:
[ ]*10:[ ]+90[ ]+nop[ ]*
@@ -32,15 +32,15 @@ Disassembly of section .text:
0+20 <nop14>:
[ ]*20:[ ]+90[ ]+nop[ ]*
[ ]*21:[ ]+90[ ]+nop[ ]*
-[ ]*22:[ ]+8d b4 26 00 00 00 00[ ]+lea[ ]+0x0\(%esi\),%esi
-[ ]*29:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi\),%edi
+[ ]*22:[ ]+8d b4 26 00 00 00 00[ ]+lea[ ]+0x0\(%esi,%eiz,1\),%esi
+[ ]*29:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi,%eiz,1\),%edi
0+30 <nop13>:
[ ]*30:[ ]+90[ ]+nop[ ]*
[ ]*31:[ ]+90[ ]+nop[ ]*
[ ]*32:[ ]+90[ ]+nop[ ]*
[ ]*33:[ ]+8d b6 00 00 00 00[ ]+lea[ ]+0x0\(%esi\),%esi
-[ ]*39:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi\),%edi
+[ ]*39:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi,%eiz,1\),%edi
0+40 <nop12>:
[ ]*40:[ ]+90[ ]+nop[ ]*
@@ -56,8 +56,8 @@ Disassembly of section .text:
[ ]*52:[ ]+90[ ]+nop[ ]*
[ ]*53:[ ]+90[ ]+nop[ ]*
[ ]*54:[ ]+90[ ]+nop[ ]*
-[ ]*55:[ ]+8d 74 26 00[ ]+lea[ ]+0x0\(%esi\),%esi
-[ ]*59:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi\),%edi
+[ ]*55:[ ]+8d 74 26 00[ ]+lea[ ]+0x0\(%esi,%eiz,1\),%esi
+[ ]*59:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi,%eiz,1\),%edi
0+60 <nop10>:
[ ]*60:[ ]+90[ ]+nop[ ]*
@@ -67,7 +67,7 @@ Disassembly of section .text:
[ ]*64:[ ]+90[ ]+nop[ ]*
[ ]*65:[ ]+90[ ]+nop[ ]*
[ ]*66:[ ]+8d 76 00[ ]+lea[ ]+0x0\(%esi\),%esi
-[ ]*69:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi\),%edi
+[ ]*69:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi,%eiz,1\),%edi
0+70 <nop9>:
[ ]*70:[ ]+90[ ]+nop[ ]*
@@ -78,7 +78,7 @@ Disassembly of section .text:
[ ]*75:[ ]+90[ ]+nop[ ]*
[ ]*76:[ ]+90[ ]+nop[ ]*
[ ]*77:[ ]+89 f6[ ]+mov[ ]+%esi,%esi
-[ ]*79:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi\),%edi
+[ ]*79:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi,%eiz,1\),%edi
0+80 <nop8>:
[ ]*80:[ ]+90[ ]+nop[ ]*
@@ -90,7 +90,7 @@ Disassembly of section .text:
[ ]*86:[ ]+90[ ]+nop[ ]*
[ ]*87:[ ]+90[ ]+nop[ ]*
[ ]*88:[ ]+90[ ]+nop[ ]*
-[ ]*89:[ ]+8d b4 26 00 00 00 00[ ]+lea[ ]+0x0\(%esi\),%esi
+[ ]*89:[ ]+8d b4 26 00 00 00 00[ ]+lea[ ]+0x0\(%esi,%eiz,1\),%esi
0+90 <nop7>:
[ ]*90:[ ]+90[ ]+nop[ ]*
@@ -102,7 +102,7 @@ Disassembly of section .text:
[ ]*96:[ ]+90[ ]+nop[ ]*
[ ]*97:[ ]+90[ ]+nop[ ]*
[ ]*98:[ ]+90[ ]+nop[ ]*
-[ ]*99:[ ]+8d b4 26 00 00 00 00[ ]+lea[ ]+0x0\(%esi\),%esi
+[ ]*99:[ ]+8d b4 26 00 00 00 00[ ]+lea[ ]+0x0\(%esi,%eiz,1\),%esi
0+a0 <nop6>:
[ ]*a0:[ ]+90[ ]+nop[ ]*
@@ -130,7 +130,7 @@ Disassembly of section .text:
[ ]*b9:[ ]+90[ ]+nop[ ]*
[ ]*ba:[ ]+90[ ]+nop[ ]*
[ ]*bb:[ ]+90[ ]+nop[ ]*
-[ ]*bc:[ ]+8d 74 26 00[ ]+lea[ ]+0x0\(%esi\),%esi
+[ ]*bc:[ ]+8d 74 26 00[ ]+lea[ ]+0x0\(%esi,%eiz,1\),%esi
0+c0 <nop4>:
[ ]*c0:[ ]+90[ ]+nop[ ]*
@@ -145,7 +145,7 @@ Disassembly of section .text:
[ ]*c9:[ ]+90[ ]+nop[ ]*
[ ]*ca:[ ]+90[ ]+nop[ ]*
[ ]*cb:[ ]+90[ ]+nop[ ]*
-[ ]*cc:[ ]+8d 74 26 00[ ]+lea[ ]+0x0\(%esi\),%esi
+[ ]*cc:[ ]+8d 74 26 00[ ]+lea[ ]+0x0\(%esi,%eiz,1\),%esi
0+d0 <nop3>:
[ ]*d0:[ ]+90[ ]+nop[ ]*
--- binutils/gas/testsuite/gas/i386/nops-2-merom.d.fake 2006-08-01 10:54:28.000000000 -0700
+++ binutils/gas/testsuite/gas/i386/nops-2-merom.d 2007-09-19 17:59:10.000000000 -0700
@@ -10,7 +10,7 @@ Disassembly of section .text:
0+ <nop>:
[ ]*0:[ ]+0f 44 c0[ ]+cmove[ ]+%eax,%eax
[ ]*3:[ ]+8d b6 00 00 00 00[ ]+lea[ ]+0x0\(%esi\),%esi
-[ ]*9:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi\),%edi
+[ ]*9:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi,%eiz,1\),%edi
0+10 <nop15>:
[ ]*10:[ ]+90[ ]+nop[ ]*
@@ -32,15 +32,15 @@ Disassembly of section .text:
0+20 <nop14>:
[ ]*20:[ ]+90[ ]+nop[ ]*
[ ]*21:[ ]+90[ ]+nop[ ]*
-[ ]*22:[ ]+8d b4 26 00 00 00 00[ ]+lea[ ]+0x0\(%esi\),%esi
-[ ]*29:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi\),%edi
+[ ]*22:[ ]+8d b4 26 00 00 00 00[ ]+lea[ ]+0x0\(%esi,%eiz,1\),%esi
+[ ]*29:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi,%eiz,1\),%edi
0+30 <nop13>:
[ ]*30:[ ]+90[ ]+nop[ ]*
[ ]*31:[ ]+90[ ]+nop[ ]*
[ ]*32:[ ]+90[ ]+nop[ ]*
[ ]*33:[ ]+8d b6 00 00 00 00[ ]+lea[ ]+0x0\(%esi\),%esi
-[ ]*39:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi\),%edi
+[ ]*39:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi,%eiz,1\),%edi
0+40 <nop12>:
[ ]*40:[ ]+90[ ]+nop[ ]*
@@ -56,8 +56,8 @@ Disassembly of section .text:
[ ]*52:[ ]+90[ ]+nop[ ]*
[ ]*53:[ ]+90[ ]+nop[ ]*
[ ]*54:[ ]+90[ ]+nop[ ]*
-[ ]*55:[ ]+8d 74 26 00[ ]+lea[ ]+0x0\(%esi\),%esi
-[ ]*59:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi\),%edi
+[ ]*55:[ ]+8d 74 26 00[ ]+lea[ ]+0x0\(%esi,%eiz,1\),%esi
+[ ]*59:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi,%eiz,1\),%edi
0+60 <nop10>:
[ ]*60:[ ]+90[ ]+nop[ ]*
@@ -67,7 +67,7 @@ Disassembly of section .text:
[ ]*64:[ ]+90[ ]+nop[ ]*
[ ]*65:[ ]+90[ ]+nop[ ]*
[ ]*66:[ ]+8d 76 00[ ]+lea[ ]+0x0\(%esi\),%esi
-[ ]*69:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi\),%edi
+[ ]*69:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi,%eiz,1\),%edi
0+70 <nop9>:
[ ]*70:[ ]+90[ ]+nop[ ]*
@@ -78,7 +78,7 @@ Disassembly of section .text:
[ ]*75:[ ]+90[ ]+nop[ ]*
[ ]*76:[ ]+90[ ]+nop[ ]*
[ ]*77:[ ]+89 f6[ ]+mov[ ]+%esi,%esi
-[ ]*79:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi\),%edi
+[ ]*79:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi,%eiz,1\),%edi
0+80 <nop8>:
[ ]*80:[ ]+90[ ]+nop[ ]*
@@ -90,7 +90,7 @@ Disassembly of section .text:
[ ]*86:[ ]+90[ ]+nop[ ]*
[ ]*87:[ ]+90[ ]+nop[ ]*
[ ]*88:[ ]+90[ ]+nop[ ]*
-[ ]*89:[ ]+8d b4 26 00 00 00 00[ ]+lea[ ]+0x0\(%esi\),%esi
+[ ]*89:[ ]+8d b4 26 00 00 00 00[ ]+lea[ ]+0x0\(%esi,%eiz,1\),%esi
0+90 <nop7>:
[ ]*90:[ ]+90[ ]+nop[ ]*
@@ -102,7 +102,7 @@ Disassembly of section .text:
[ ]*96:[ ]+90[ ]+nop[ ]*
[ ]*97:[ ]+90[ ]+nop[ ]*
[ ]*98:[ ]+90[ ]+nop[ ]*
-[ ]*99:[ ]+8d b4 26 00 00 00 00[ ]+lea[ ]+0x0\(%esi\),%esi
+[ ]*99:[ ]+8d b4 26 00 00 00 00[ ]+lea[ ]+0x0\(%esi,%eiz,1\),%esi
0+a0 <nop6>:
[ ]*a0:[ ]+90[ ]+nop[ ]*
@@ -130,7 +130,7 @@ Disassembly of section .text:
[ ]*b9:[ ]+90[ ]+nop[ ]*
[ ]*ba:[ ]+90[ ]+nop[ ]*
[ ]*bb:[ ]+90[ ]+nop[ ]*
-[ ]*bc:[ ]+8d 74 26 00[ ]+lea[ ]+0x0\(%esi\),%esi
+[ ]*bc:[ ]+8d 74 26 00[ ]+lea[ ]+0x0\(%esi,%eiz,1\),%esi
0+c0 <nop4>:
[ ]*c0:[ ]+90[ ]+nop[ ]*
@@ -145,7 +145,7 @@ Disassembly of section .text:
[ ]*c9:[ ]+90[ ]+nop[ ]*
[ ]*ca:[ ]+90[ ]+nop[ ]*
[ ]*cb:[ ]+90[ ]+nop[ ]*
-[ ]*cc:[ ]+8d 74 26 00[ ]+lea[ ]+0x0\(%esi\),%esi
+[ ]*cc:[ ]+8d 74 26 00[ ]+lea[ ]+0x0\(%esi,%eiz,1\),%esi
0+d0 <nop3>:
[ ]*d0:[ ]+90[ ]+nop[ ]*
--- binutils/gas/testsuite/gas/i386/nops-2.d.fake 2006-08-01 10:54:28.000000000 -0700
+++ binutils/gas/testsuite/gas/i386/nops-2.d 2007-09-19 17:59:10.000000000 -0700
@@ -9,7 +9,7 @@ Disassembly of section .text:
0+ <nop>:
[ ]*0:[ ]+0f 44 c0[ ]+cmove[ ]+%eax,%eax
[ ]*3:[ ]+8d b6 00 00 00 00[ ]+lea[ ]+0x0\(%esi\),%esi
-[ ]*9:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi\),%edi
+[ ]*9:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi,%eiz,1\),%edi
0+10 <nop15>:
[ ]*10:[ ]+90[ ]+nop[ ]*
@@ -31,15 +31,15 @@ Disassembly of section .text:
0+20 <nop14>:
[ ]*20:[ ]+90[ ]+nop[ ]*
[ ]*21:[ ]+90[ ]+nop[ ]*
-[ ]*22:[ ]+8d b4 26 00 00 00 00[ ]+lea[ ]+0x0\(%esi\),%esi
-[ ]*29:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi\),%edi
+[ ]*22:[ ]+8d b4 26 00 00 00 00[ ]+lea[ ]+0x0\(%esi,%eiz,1\),%esi
+[ ]*29:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi,%eiz,1\),%edi
0+30 <nop13>:
[ ]*30:[ ]+90[ ]+nop[ ]*
[ ]*31:[ ]+90[ ]+nop[ ]*
[ ]*32:[ ]+90[ ]+nop[ ]*
[ ]*33:[ ]+8d b6 00 00 00 00[ ]+lea[ ]+0x0\(%esi\),%esi
-[ ]*39:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi\),%edi
+[ ]*39:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi,%eiz,1\),%edi
0+40 <nop12>:
[ ]*40:[ ]+90[ ]+nop[ ]*
@@ -55,8 +55,8 @@ Disassembly of section .text:
[ ]*52:[ ]+90[ ]+nop[ ]*
[ ]*53:[ ]+90[ ]+nop[ ]*
[ ]*54:[ ]+90[ ]+nop[ ]*
-[ ]*55:[ ]+8d 74 26 00[ ]+lea[ ]+0x0\(%esi\),%esi
-[ ]*59:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi\),%edi
+[ ]*55:[ ]+8d 74 26 00[ ]+lea[ ]+0x0\(%esi,%eiz,1\),%esi
+[ ]*59:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi,%eiz,1\),%edi
0+60 <nop10>:
[ ]*60:[ ]+90[ ]+nop[ ]*
@@ -66,7 +66,7 @@ Disassembly of section .text:
[ ]*64:[ ]+90[ ]+nop[ ]*
[ ]*65:[ ]+90[ ]+nop[ ]*
[ ]*66:[ ]+8d 76 00[ ]+lea[ ]+0x0\(%esi\),%esi
-[ ]*69:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi\),%edi
+[ ]*69:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi,%eiz,1\),%edi
0+70 <nop9>:
[ ]*70:[ ]+90[ ]+nop[ ]*
@@ -77,7 +77,7 @@ Disassembly of section .text:
[ ]*75:[ ]+90[ ]+nop[ ]*
[ ]*76:[ ]+90[ ]+nop[ ]*
[ ]*77:[ ]+89 f6[ ]+mov[ ]+%esi,%esi
-[ ]*79:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi\),%edi
+[ ]*79:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi,%eiz,1\),%edi
0+80 <nop8>:
[ ]*80:[ ]+90[ ]+nop[ ]*
@@ -89,7 +89,7 @@ Disassembly of section .text:
[ ]*86:[ ]+90[ ]+nop[ ]*
[ ]*87:[ ]+90[ ]+nop[ ]*
[ ]*88:[ ]+90[ ]+nop[ ]*
-[ ]*89:[ ]+8d b4 26 00 00 00 00[ ]+lea[ ]+0x0\(%esi\),%esi
+[ ]*89:[ ]+8d b4 26 00 00 00 00[ ]+lea[ ]+0x0\(%esi,%eiz,1\),%esi
0+90 <nop7>:
[ ]*90:[ ]+90[ ]+nop[ ]*
@@ -101,7 +101,7 @@ Disassembly of section .text:
[ ]*96:[ ]+90[ ]+nop[ ]*
[ ]*97:[ ]+90[ ]+nop[ ]*
[ ]*98:[ ]+90[ ]+nop[ ]*
-[ ]*99:[ ]+8d b4 26 00 00 00 00[ ]+lea[ ]+0x0\(%esi\),%esi
+[ ]*99:[ ]+8d b4 26 00 00 00 00[ ]+lea[ ]+0x0\(%esi,%eiz,1\),%esi
0+a0 <nop6>:
[ ]*a0:[ ]+90[ ]+nop[ ]*
@@ -129,7 +129,7 @@ Disassembly of section .text:
[ ]*b9:[ ]+90[ ]+nop[ ]*
[ ]*ba:[ ]+90[ ]+nop[ ]*
[ ]*bb:[ ]+90[ ]+nop[ ]*
-[ ]*bc:[ ]+8d 74 26 00[ ]+lea[ ]+0x0\(%esi\),%esi
+[ ]*bc:[ ]+8d 74 26 00[ ]+lea[ ]+0x0\(%esi,%eiz,1\),%esi
0+c0 <nop4>:
[ ]*c0:[ ]+90[ ]+nop[ ]*
@@ -144,7 +144,7 @@ Disassembly of section .text:
[ ]*c9:[ ]+90[ ]+nop[ ]*
[ ]*ca:[ ]+90[ ]+nop[ ]*
[ ]*cb:[ ]+90[ ]+nop[ ]*
-[ ]*cc:[ ]+8d 74 26 00[ ]+lea[ ]+0x0\(%esi\),%esi
+[ ]*cc:[ ]+8d 74 26 00[ ]+lea[ ]+0x0\(%esi,%eiz,1\),%esi
0+d0 <nop3>:
[ ]*d0:[ ]+90[ ]+nop[ ]*
--- binutils/gas/testsuite/gas/i386/nops-3-i386.d.fake 2007-07-23 13:03:23.000000000 -0700
+++ binutils/gas/testsuite/gas/i386/nops-3-i386.d 2007-09-19 17:59:10.000000000 -0700
@@ -40,6 +40,6 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 90 nop
[ ]*[a-f0-9]+: 90 nop
[ ]*[a-f0-9]+: 89 c3 mov %eax,%ebx
-[ ]*[a-f0-9]+: 8d b4 26 00 00 00 00 lea 0x0\(%esi\),%esi
-[ ]*[a-f0-9]+: 8d bc 27 00 00 00 00 lea 0x0\(%edi\),%edi
+[ ]*[a-f0-9]+: 8d b4 26 00 00 00 00 lea 0x0\(%esi,%eiz,1\),%esi
+[ ]*[a-f0-9]+: 8d bc 27 00 00 00 00 lea 0x0\(%edi,%eiz,1\),%edi
#pass
--- binutils/gas/testsuite/gas/i386/nops-3.d.fake 2007-07-24 15:03:59.000000000 -0700
+++ binutils/gas/testsuite/gas/i386/nops-3.d 2007-09-19 17:59:10.000000000 -0700
@@ -39,6 +39,6 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 90 nop
[ ]*[a-f0-9]+: 90 nop
[ ]*[a-f0-9]+: 89 c3 mov %eax,%ebx
-[ ]*[a-f0-9]+: 8d b4 26 00 00 00 00 lea 0x0\(%esi\),%esi
-[ ]*[a-f0-9]+: 8d bc 27 00 00 00 00 lea 0x0\(%edi\),%edi
+[ ]*[a-f0-9]+: 8d b4 26 00 00 00 00 lea 0x0\(%esi,%eiz,1\),%esi
+[ ]*[a-f0-9]+: 8d bc 27 00 00 00 00 lea 0x0\(%edi,%eiz,1\),%edi
#pass
--- binutils/gas/testsuite/gas/i386/sib-intel.d.fake 2007-09-20 08:55:38.000000000 -0700
+++ binutils/gas/testsuite/gas/i386/sib-intel.d 2007-09-20 09:13:44.000000000 -0700
@@ -0,0 +1,20 @@
+#source: sib.s
+#objdump: -dw -Mintel
+#name: i386 SIB (Intel mode)
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <foo>:
+[ ]*[a-f0-9]+: 8b 03 mov eax,DWORD PTR \[ebx\]
+[ ]*[a-f0-9]+: 8b 04 23 mov eax,DWORD PTR \[ebx\+eiz\*1\]
+[ ]*[a-f0-9]+: 8b 04 63 mov eax,DWORD PTR \[ebx\+eiz\*2\]
+[ ]*[a-f0-9]+: 8b 04 a3 mov eax,DWORD PTR \[ebx\+eiz\*4\]
+[ ]*[a-f0-9]+: 8b 04 e3 mov eax,DWORD PTR \[ebx\+eiz\*8\]
+[ ]*[a-f0-9]+: 8b 04 24 mov eax,DWORD PTR \[esp\]
+[ ]*[a-f0-9]+: 8b 04 24 mov eax,DWORD PTR \[esp\]
+[ ]*[a-f0-9]+: 8b 04 64 mov eax,DWORD PTR \[esp\+eiz\*2\]
+[ ]*[a-f0-9]+: 8b 04 a4 mov eax,DWORD PTR \[esp\+eiz\*4\]
+[ ]*[a-f0-9]+: 8b 04 e4 mov eax,DWORD PTR \[esp\+eiz\*8\]
+#pass
--- binutils/gas/testsuite/gas/i386/sib.d.fake 2005-01-12 11:12:51.000000000 -0800
+++ binutils/gas/testsuite/gas/i386/sib.d 2007-09-20 09:13:38.000000000 -0700
@@ -5,11 +5,15 @@
Disassembly of section .text:
-0+000 <foo>:
- 0: 8b 04 23 [ ]*mov [ ]*\(%ebx\),%eax
- 3: 8b 04 63 [ ]*mov [ ]*\(%ebx\),%eax
- 6: 8b 04 a3 [ ]*mov [ ]*\(%ebx\),%eax
- 9: 8b 04 e3 [ ]*mov [ ]*\(%ebx\),%eax
- c: 90 [ ]*nop [ ]*
- d: 90 [ ]*nop [ ]*
- ...
+0+ <foo>:
+[ ]*[a-f0-9]+: 8b 03 mov \(%ebx\),%eax
+[ ]*[a-f0-9]+: 8b 04 23 mov \(%ebx,%eiz,1\),%eax
+[ ]*[a-f0-9]+: 8b 04 63 mov \(%ebx,%eiz,2\),%eax
+[ ]*[a-f0-9]+: 8b 04 a3 mov \(%ebx,%eiz,4\),%eax
+[ ]*[a-f0-9]+: 8b 04 e3 mov \(%ebx,%eiz,8\),%eax
+[ ]*[a-f0-9]+: 8b 04 24 mov \(%esp\),%eax
+[ ]*[a-f0-9]+: 8b 04 24 mov \(%esp\),%eax
+[ ]*[a-f0-9]+: 8b 04 64 mov \(%esp,%eiz,2\),%eax
+[ ]*[a-f0-9]+: 8b 04 a4 mov \(%esp,%eiz,4\),%eax
+[ ]*[a-f0-9]+: 8b 04 e4 mov \(%esp,%eiz,8\),%eax
+#pass
--- binutils/gas/testsuite/gas/i386/sib.s.fake 2005-01-12 11:12:51.000000000 -0800
+++ binutils/gas/testsuite/gas/i386/sib.s 2007-09-19 15:46:48.000000000 -0700
@@ -1,11 +1,16 @@
#Test the special case of the index bits, 0x4, in SIB.
.text
+ .allow_index_reg
foo:
- .byte 0x8B, 0x04, 0x23 # effect is: movl (%ebx), %eax
- .byte 0x8B, 0x04, 0x63 # effect is: movl (%ebx), %eax
- .byte 0x8B, 0x04, 0xA3 # effect is: movl (%ebx), %eax
- .byte 0x8B, 0x04, 0xE3 # effect is: movl (%ebx), %eax
- nop
- nop
- .p2align 4,0
+ mov (%ebx),%eax
+ mov (%ebx,%eiz,1),%eax
+ mov (%ebx,%eiz,2),%eax
+ mov (%ebx,%eiz,4),%eax
+ mov (%ebx,%eiz,8),%eax
+ mov (%esp),%eax
+ mov (%esp,%eiz,1),%eax
+ mov (%esp,%eiz,2),%eax
+ mov (%esp,%eiz,4),%eax
+ mov (%esp,%eiz,8),%eax
+ .p2align 4
--- binutils/gas/testsuite/gas/i386/x86-64-sib-intel.d.fake 2007-09-20 09:10:01.000000000 -0700
+++ binutils/gas/testsuite/gas/i386/x86-64-sib-intel.d 2007-09-20 09:13:18.000000000 -0700
@@ -0,0 +1,21 @@
+#source: x86-64-sib.s
+#as: -J
+#objdump: -dw -Mintel
+#name: x86-64 SIB (Intel mode)
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <foo>:
+[ ]*[a-f0-9]+: 8b 03 mov eax,DWORD PTR \[rbx\]
+[ ]*[a-f0-9]+: 8b 04 23 mov eax,DWORD PTR \[rbx\+riz\*1\]
+[ ]*[a-f0-9]+: 8b 04 63 mov eax,DWORD PTR \[rbx\+riz\*2\]
+[ ]*[a-f0-9]+: 8b 04 a3 mov eax,DWORD PTR \[rbx\+riz\*4\]
+[ ]*[a-f0-9]+: 8b 04 e3 mov eax,DWORD PTR \[rbx\+riz\*8\]
+[ ]*[a-f0-9]+: 8b 04 24 mov eax,DWORD PTR \[rsp\]
+[ ]*[a-f0-9]+: 8b 04 24 mov eax,DWORD PTR \[rsp\]
+[ ]*[a-f0-9]+: 8b 04 64 mov eax,DWORD PTR \[rsp\+riz\*2\]
+[ ]*[a-f0-9]+: 8b 04 a4 mov eax,DWORD PTR \[rsp\+riz\*4\]
+[ ]*[a-f0-9]+: 8b 04 e4 mov eax,DWORD PTR \[rsp\+riz\*8\]
+#pass
--- binutils/gas/testsuite/gas/i386/x86-64-sib.d.fake 2007-09-20 09:09:56.000000000 -0700
+++ binutils/gas/testsuite/gas/i386/x86-64-sib.d 2007-09-20 09:13:31.000000000 -0700
@@ -0,0 +1,20 @@
+#as: -J
+#objdump: -dw
+#name: x86-64 SIB
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <foo>:
+[ ]*[a-f0-9]+: 8b 03 mov \(%rbx\),%eax
+[ ]*[a-f0-9]+: 8b 04 23 mov \(%rbx,%riz,1\),%eax
+[ ]*[a-f0-9]+: 8b 04 63 mov \(%rbx,%riz,2\),%eax
+[ ]*[a-f0-9]+: 8b 04 a3 mov \(%rbx,%riz,4\),%eax
+[ ]*[a-f0-9]+: 8b 04 e3 mov \(%rbx,%riz,8\),%eax
+[ ]*[a-f0-9]+: 8b 04 24 mov \(%rsp\),%eax
+[ ]*[a-f0-9]+: 8b 04 24 mov \(%rsp\),%eax
+[ ]*[a-f0-9]+: 8b 04 64 mov \(%rsp,%riz,2\),%eax
+[ ]*[a-f0-9]+: 8b 04 a4 mov \(%rsp,%riz,4\),%eax
+[ ]*[a-f0-9]+: 8b 04 e4 mov \(%rsp,%riz,8\),%eax
+#pass
--- binutils/gas/testsuite/gas/i386/x86-64-sib.s.fake 2007-09-20 09:09:52.000000000 -0700
+++ binutils/gas/testsuite/gas/i386/x86-64-sib.s 2007-09-20 09:11:12.000000000 -0700
@@ -0,0 +1,16 @@
+#Test the special case of the index bits, 0x4, in SIB.
+
+ .text
+ .allow_index_reg
+foo:
+ mov (%rbx),%eax
+ mov (%rbx,%riz,1),%eax
+ mov (%rbx,%riz,2),%eax
+ mov (%rbx,%riz,4),%eax
+ mov (%rbx,%riz,8),%eax
+ mov (%rsp),%eax
+ mov (%rsp,%riz,1),%eax
+ mov (%rsp,%riz,2),%eax
+ mov (%rsp,%riz,4),%eax
+ mov (%rsp,%riz,8),%eax
+ .p2align 4
--- binutils/ld/testsuite/ld-i386/tlsbin.dd.fake 2007-08-23 09:13:57.000000000 -0700
+++ binutils/ld/testsuite/ld-i386/tlsbin.dd 2007-09-19 18:00:05.000000000 -0700
@@ -92,7 +92,7 @@ Disassembly of section .text:
# LD -> LE
8049085: 65 a1 00 00 00 00[ ]+mov %gs:0x0,%eax
804908b: 90[ ]+nop *
- 804908c: 8d 74 26 00[ ]+lea 0x0\(%esi\),%esi
+ 804908c: 8d 74 26 00[ ]+lea 0x0\(%esi,%eiz,1\),%esi
8049090: 90[ ]+nop *
8049091: 90[ ]+nop *
8049092: 8d 90 20 f0 ff ff[ ]+lea -0xfe0\(%eax\),%edx
@@ -108,7 +108,7 @@ Disassembly of section .text:
# LD -> LE against hidden variables
80490a4: 65 a1 00 00 00 00[ ]+mov %gs:0x0,%eax
80490aa: 90[ ]+nop *
- 80490ab: 8d 74 26 00[ ]+lea 0x0\(%esi\),%esi
+ 80490ab: 8d 74 26 00[ ]+lea 0x0\(%esi,%eiz,1\),%esi
80490af: 90[ ]+nop *
80490b0: 90[ ]+nop *
80490b1: 8d 90 40 f0 ff ff[ ]+lea -0xfc0\(%eax\),%edx
--- binutils/ld/testsuite/ld-i386/tlsld1.dd.fake 2007-08-14 12:48:20.000000000 -0700
+++ binutils/ld/testsuite/ld-i386/tlsld1.dd 2007-09-19 18:00:05.000000000 -0700
@@ -11,5 +11,5 @@ Disassembly of section .text:
[a-f0-9]+ <_start>:
[ ]*[a-f0-9]+: 65 a1 00 00 00 00 mov %gs:0x0,%eax
[ ]*[a-f0-9]+: 90 nop
-[ ]*[a-f0-9]+: 8d 74 26 00 lea 0x0\(%esi\),%esi
+[ ]*[a-f0-9]+: 8d 74 26 00 lea 0x0\(%esi,%eiz,1\),%esi
#pass
--- binutils/opcodes/i386-dis.c.fake 2007-09-19 12:44:05.000000000 -0700
+++ binutils/opcodes/i386-dis.c 2007-09-19 17:56:30.000000000 -0700
@@ -1353,6 +1353,8 @@ static const char **names16;
static const char **names8;
static const char **names8rex;
static const char **names_seg;
+static const char *index64;
+static const char *index32;
static const char **index16;
static const char *intel_names64[] = {
@@ -1377,6 +1379,8 @@ static const char *intel_names8rex[] = {
static const char *intel_names_seg[] = {
"es", "cs", "ss", "ds", "fs", "gs", "?", "?",
};
+static const char *intel_index64 = "riz";
+static const char *intel_index32 = "eiz";
static const char *intel_index16[] = {
"bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
};
@@ -1403,6 +1407,8 @@ static const char *att_names8rex[] = {
static const char *att_names_seg[] = {
"%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
};
+static const char *att_index64 = "%riz";
+static const char *att_index32 = "%eiz";
static const char *att_index16[] = {
"%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
};
@@ -5001,6 +5007,8 @@ print_insn (bfd_vma pc, disassemble_info
names8 = intel_names8;
names8rex = intel_names8rex;
names_seg = intel_names_seg;
+ index64 = intel_index64;
+ index32 = intel_index32;
index16 = intel_index16;
open_char = '[';
close_char = ']';
@@ -5015,6 +5023,8 @@ print_insn (bfd_vma pc, disassemble_info
names8 = att_names8;
names8rex = att_names8rex;
names_seg = att_names_seg;
+ index64 = att_index64;
+ index32 = att_index32;
index16 = att_index16;
open_char = '(';
close_char = ')';
@@ -6318,9 +6328,7 @@ OP_E_extended (int bytemode, int sizefla
havesib = 1;
FETCH_DATA (the_info, codep + 1);
index = (*codep >> 3) & 7;
- if (address_mode == mode_64bit || index != 0x4)
- /* When INDEX == 0x4 in 32 bit mode, SCALE is ignored. */
- scale = (*codep >> 6) & 3;
+ scale = (*codep >> 6) & 3;
base = *codep & 7;
USED_REX (REX_X);
if (rex & REX_X)
@@ -6391,19 +6399,26 @@ OP_E_extended (int bytemode, int sizefla
? names64[base] : names32[base]);
if (havesib)
{
- if (haveindex)
+ /* ESP/RSP won't allow index. If base isn't ESP/RSP,
+ print index to tell base + index from base. */
+ if (scale != 0
+ || haveindex
+ || (havebase && base != ESP_REG_NUM))
{
if (!intel_syntax || havebase)
{
*obufp++ = separator_char;
*obufp = '\0';
}
- oappend (address_mode == mode_64bit
- && (sizeflag & AFLAG)
- ? names64[index] : names32[index]);
- }
- if (scale != 0 || haveindex)
- {
+ if (haveindex)
+ oappend (address_mode == mode_64bit
+ && (sizeflag & AFLAG)
+ ? names64[index] : names32[index]);
+ else
+ oappend (address_mode == mode_64bit
+ && (sizeflag & AFLAG)
+ ? index64 : index32);
+
*obufp++ = scale_char;
*obufp = '\0';
sprintf (scratchbuf, "%d", 1 << scale);
@@ -6413,7 +6428,7 @@ OP_E_extended (int bytemode, int sizefla
if (intel_syntax
&& (disp || modrm.mod != 0 || (base & 7) == 5))
{
- if ((bfd_signed_vma) disp >= 0)
+ if (!havedisp || (bfd_signed_vma) disp >= 0)
{
*obufp++ = '+';
*obufp = '\0';
@@ -6425,7 +6440,10 @@ OP_E_extended (int bytemode, int sizefla
disp = - (bfd_signed_vma) disp;
}
- print_displacement (scratchbuf, disp);
+ if (havedisp)
+ print_displacement (scratchbuf, disp);
+ else
+ print_operand_value (scratchbuf, 1, disp);
oappend (scratchbuf);
}
--- binutils/opcodes/i386-opc.h.fake 2007-09-19 10:01:40.000000000 -0700
+++ binutils/opcodes/i386-opc.h 2007-09-19 15:46:48.000000000 -0700
@@ -444,6 +444,9 @@ typedef struct
#define RegRex64 0x2 /* Extended 8 bit register. */
unsigned int reg_num;
#define RegRip ((unsigned int ) ~0)
+/* EIZ and RIZ are fake index registers. */
+#define RegEiz (RegRip - 1)
+#define RegRiz (RegEiz - 1)
}
reg_entry;
--- binutils/opcodes/i386-reg.tbl.fake 2007-09-19 10:01:40.000000000 -0700
+++ binutils/opcodes/i386-reg.tbl 2007-09-19 15:46:48.000000000 -0700
@@ -190,6 +190,10 @@ xmm15, RegXMM, RegRex, 7
// No type will make this register rejected for all purposes except
// for addressing. This saves creating one extra type for RIP.
rip, BaseIndex, 0, RegRip
+// No type will make these registers rejected for all purposes except
+// for addressing.
+eiz, BaseIndex, 0, RegEiz
+riz, BaseIndex, 0, RegRiz
// fp regs.
st(0), FloatReg|FloatAcc, 0, 0
st(1), FloatReg, 0, 1
--- binutils/opcodes/i386-tbl.h.fake 2007-09-19 12:44:56.000000000 -0700
+++ binutils/opcodes/i386-tbl.h 2007-09-19 15:46:48.000000000 -0700
@@ -13279,6 +13279,14 @@ const reg_entry i386_regtab[] =
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
0, RegRip },
+ { "eiz",
+ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+ 0, RegEiz },
+ { "riz",
+ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+ 0, RegRiz },
{ "st(0)",
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 } },