RE: [PATCH] Add x86 SSE5 instructions to the GNU binary utilities

["Meissner, Michael" <michael dot meissner at amd dot com>]

The problem is move test register is/was:
	0f 24 modrm

Where the top 2 bits of modrm are 11 to encode register/register move
(move test was only defined for registers).  The SSE5 4 argument
instructions use:
	0f 24 opcode

There are no SSE5 instructions with the 2 bits sets in the 0f 24 opcode
field.  You either have to duplicate a lot of 3 byte or MODRM if you do
it in a table fashion like you suggest.  It is much simpler to just do
the test, and reuse the rest of the dissembler for modrm (in the case of
move test) or 3 byte opcode (in the case of SSE5).

--
Michael Meissner
AMD, MS 83-29
90 Central Street
Boxborough, MA 01719

> -----Original Message-----
> From: H.J. Lu [mailto:hjl@lucon.org]
> Sent: Thursday, September 13, 2007 4:38 PM
> To: rajagopal, dwarak
> Cc: binutils@sourceware.org; Meissner, Michael; Harle, Christophe
> Subject: Re: [PATCH] Add x86 SSE5 instructions to the GNU binary
utilities
> 
> On Thu, Sep 13, 2007 at 03:08:54PM -0500, rajagopal, dwarak wrote:
> > The enclosed patch adds support for the SSE5 instructions to the
> > assembler and disassembler.
> >
> > I have made changes to the original patch so that it uses bitfields
(the
> > new infrastructure changes which H.J had checked in last week) for
> > cpu_flag, opcode_modifier and operand_types for the new
instructions.
> >
> 
> Did SSE5 reuse the same opcode for move test registers? If not,
> please don't remove OPC_EXT_45. You can use
> 
> {
>   /* OPC_EXT_45 */
>   { THREE_BYTE_SSE5_0F7A }
>   { "movL",          { Td, Rd } },
> }
> 
> 
> H.J.
>