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ARM disassembler crash
- From: Paul Brook <paul at codesourcery dot com>
- To: binutils at sourceware dot org
- Date: Sat, 24 Mar 2007 02:50:44 +0000
- Subject: ARM disassembler crash
The attached patch fixes a crash when disassembling unusual forms of the ARM
VFP fmrx and fmxr instructions. The opcode table contains %<bitfield>x, but
this was not implemented by print_insn_coprocessor.
Tested with cross to arm-none-eabi.
Applied to head.
Paul
2007-03-24 Paul Brook <paul@codesourcery.com>
opcodes/
* arm-dis.c (coprocessor_opcodes): Remove superfluous 0x.
(print_insn_coprocessor): Handle %<bitfield>x.
Index: opcodes/arm-dis.c
===================================================================
--- opcodes/arm-dis.c (revision 166694)
+++ opcodes/arm-dis.c (working copy)
@@ -279,8 +279,8 @@ static const struct opcode32 coprocessor
{FPU_VFP_EXT_V1, 0x0e100b10, 0x0ff00fff, "fmrdl%c\t%12-15r, %z2"},
{FPU_VFP_EXT_V1, 0x0e200b10, 0x0ff00fff, "fmdhr%c\t%z2, %12-15r"},
{FPU_VFP_EXT_V1, 0x0e300b10, 0x0ff00fff, "fmrdh%c\t%12-15r, %z2"},
- {FPU_VFP_EXT_V1xD, 0x0ee00a10, 0x0ff00fff, "fmxr%c\t<impl def 0x%16-19x>, %12-15r"},
- {FPU_VFP_EXT_V1xD, 0x0ef00a10, 0x0ff00fff, "fmrx%c\t%12-15r, <impl def 0x%16-19x>"},
+ {FPU_VFP_EXT_V1xD, 0x0ee00a10, 0x0ff00fff, "fmxr%c\t<impl def %16-19x>, %12-15r"},
+ {FPU_VFP_EXT_V1xD, 0x0ef00a10, 0x0ff00fff, "fmrx%c\t%12-15r, <impl def %16-19x>"},
{FPU_VFP_EXT_V1xD, 0x0e000a10, 0x0ff00f7f, "fmsr%c\t%y2, %12-15r"},
{FPU_VFP_EXT_V1xD, 0x0e100a10, 0x0ff00f7f, "fmrs%c\t%12-15r, %y2"},
{FPU_VFP_EXT_V1xD, 0x0eb50a40, 0x0fbf0f70, "fcmp%7'ezs%c\t%y1"},
@@ -1862,6 +1862,11 @@ print_insn_coprocessor (bfd_vma pc, stru
case 'G':
func (stream, "%s", iwmmxt_cregnames[value]);
break;
+
+ case 'x':
+ func (stream, "0x%lx", value);
+ break;
+
case '`':
c++;
if (value == 0)