[patch] ldr reg,=N for Thumb-2

[Paul Brook <paul at codesourcery dot com>]

The attached below implements the "ldr reg, =N" pseudo-op Thumb unified 
assembly.

Tested with cross to arm-none-eabi.
Ok?

Paul

2006-03-13  Paul Brook  <paul@codesourcery.com>

gas/
	* config/tc-arm.c (THUMB2_LOAD_BIT): Define.
	(move_or_literal_pool): Handle 32-bit Thumb instructions.
	(do_t_ldst): Call move_or_literal_pool for =N addressing modes.
gas/testsuite/
	* gas/arm/thumb2_pool.d: New test.
	* gas/arm/thumb2_pool.s: New test.

Index: gas/config/tc-arm.c
===================================================================
RCS file: /var/cvsroot/src-cvs/src/gas/config/tc-arm.c,v
retrieving revision 1.246
diff -u -p -r1.246 tc-arm.c
--- gas/config/tc-arm.c	10 Mar 2006 17:20:30 -0000	1.246
+++ gas/config/tc-arm.c	13 Mar 2006 22:22:17 -0000
@@ -560,6 +560,7 @@ struct asm_opcode
 #define THUMB_SIZE	2	/* Size of thumb instruction.  */
 #define THUMB_PP_PC_LR 0x0100
 #define THUMB_LOAD_BIT 0x0800
+#define THUMB2_LOAD_BIT 0x00100000
 
 #define BAD_ARGS	_("bad arguments to instruction")
 #define BAD_PC		_("r15 not allowed here")
@@ -4441,7 +4442,14 @@ encode_arm_cp_address (int i, int wb_ok,
 static int
 move_or_literal_pool (int i, bfd_boolean thumb_p, bfd_boolean mode_3)
 {
-  if ((inst.instruction & (thumb_p ? THUMB_LOAD_BIT : LOAD_BIT)) == 0)
+  unsigned long tbit;
+
+  if (thumb_p)
+    tbit = (inst.instruction > 0xffff) ? THUMB2_LOAD_BIT : THUMB_LOAD_BIT;
+  else
+    tbit = LOAD_BIT;
+
+  if ((inst.instruction & tbit) == 0)
     {
       inst.error = _("invalid pseudo operation");
       return 1;
@@ -4455,7 +4463,7 @@ move_or_literal_pool (int i, bfd_boolean
     {
       if (thumb_p)
 	{
-	  if ((inst.reloc.exp.X_add_number & ~0xFF) == 0)
+	  if (!unified_syntax && (inst.reloc.exp.X_add_number & ~0xFF) == 0)
 	    {
 	      /* This can be done with a mov(1) instruction.  */
 	      inst.instruction	= T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8);
@@ -5963,7 +5971,7 @@ encode_thumb32_addr_mode (int i, bfd_boo
   bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
 
   constraint (!inst.operands[i].isreg,
-	      _("Thumb does not support the ldr =N pseudo-operation"));
+	      _("Instruction does not support the =N addresses"));
 
   inst.instruction |= inst.operands[i].reg << 16;
   if (inst.operands[i].immisreg)
@@ -6948,6 +6956,13 @@ do_t_ldst (void)
   opcode = inst.instruction;
   if (unified_syntax)
     {
+      if (!inst.operands[1].isreg)
+	{
+	  if (opcode <= 0xffff)
+	    inst.instruction = THUMB_OP32 (opcode);
+	  if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE))
+	    return;
+	}
       if (inst.operands[1].isreg
 	  && !inst.operands[1].writeback
 	  && !inst.operands[1].shifted && !inst.operands[1].postind
Index: gas/testsuite/gas/arm/thumb2_pool.d
===================================================================
RCS file: gas/testsuite/gas/arm/thumb2_pool.d
diff -N gas/testsuite/gas/arm/thumb2_pool.d
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ gas/testsuite/gas/arm/thumb2_pool.d	13 Mar 2006 22:17:46 -0000
@@ -0,0 +1,15 @@
+# as: -march=armv6t2
+# objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0+000 <[^>]+> 4e04      	ldr	r6, \[pc, #16\]	\(00+14 <[^>]+>\)
+0+002 <[^>]+> 4904      	ldr	r1, \[pc, #16\]	\(00+14 <[^>]+>\)
+0+004 <[^>]+> f8df 600c 	ldr\.w	r6, \[pc, #12\]	; 00+14 <[^>]+>
+0+008 <[^>]+> f8df 9008 	ldr\.w	r9, \[pc, #8\]	; 00+14 <[^>]+>
+0+00c <[^>]+> bf00      	nop
+0+00e <[^>]+> f8df 5004 	ldr\.w	r5, \[pc, #4\]	; 00+14 <[^>]+>
+0+012 <[^>]+> 4900      	ldr	r1, \[pc, #0\]	\(00+14 <[^>]+>\)
+0+014 <[^>]+> (5678|1234) .*
+0+016 <[^>]+> (1234|5678) .*
Index: gas/testsuite/gas/arm/thumb2_pool.s
===================================================================
RCS file: gas/testsuite/gas/arm/thumb2_pool.s
diff -N gas/testsuite/gas/arm/thumb2_pool.s
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ gas/testsuite/gas/arm/thumb2_pool.s	13 Mar 2006 22:03:07 -0000
@@ -0,0 +1,13 @@
+	.text
+	.thumb
+	.syntax unified
+	.thumb_func
+thumb2_ldr:
+	ldr	r6, =0x12345678
+	ldr.n	r1, =0x12345678
+	ldr.w	r6, =0x12345678
+	ldr	r9, =0x12345678
+	nop
+	ldr.w	r5, =0x12345678
+	ldr	r1, =0x12345678
+	.pool