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[m32c] new relocs, pointer bugfix.
- From: DJ Delorie <dj at redhat dot com>
- To: binutils at sources dot redhat dot com
- Date: Mon, 25 Jul 2005 23:21:29 -0400
- Subject: [m32c] new relocs, pointer bugfix.
While working on the m32c libgloss, I realized we had no way of
loading large addresses on the R8C/M16C (they have a 20 bit address
space, but no 20 bit constants) so I added some modifiers and relocs
to support that kind of thing. While I was at it I cleaned up the
unused BFD_RELOC_* entries and fixed the pointer problem Alan posted.
[bfd]
* reloc.c: Remove unused M32C relocs, add BFD_RELOC_M32C_HI8.
* libbfd.h: Regenerate.
* bfd-in2.h: Regenerate.
* elf32-m32c.c (m32c_elf_howto_table): Add R_M32C_8, R_M32C_LO16,
R_M32C_HI8, R_M32C_HI16.
(m32c_reloc_map): Likewise.
(m32c_elf_relocate_section): Add R_M32C_HI8 and R_M32C_HI16.
[cpu]
* m32c.opc (parse_unsigned8): Add %dsp8().
(parse_signed8): Add %hi8().
(parse_unsigned16): Add %dsp16().
(parse_signed16): Add %lo16() and %hi16().
(parse_lab_5_3): Make valuep a bfd_vma *.
[gas]
* config/tc-m32c.c (md_cgen_lookup_reloc): Add 8 bit operands.
Support %mod() modifiers from opcodes.
* doc/c-m32c.texi (M32C-Modifiers): New section.
[include/elf]
* m32c.h: Add R_M32C_8, R_M32C_LO16, R_M32C_HI8, and R_M32C_HI16.
[opcodes]
* m32c-asm.c Regenerate.
* m32c-dis.c Regenerate.
Index: bfd/elf32-m32c.c
===================================================================
RCS file: /cvs/src/src/bfd/elf32-m32c.c,v
retrieving revision 1.1
diff -p -U3 -r1.1 elf32-m32c.c
--- bfd/elf32-m32c.c 14 Jul 2005 22:51:55 -0000 1.1
+++ bfd/elf32-m32c.c 26 Jul 2005 02:22:47 -0000
@@ -132,6 +132,62 @@ static reloc_howto_type m32c_elf_howto_t
0, /* src_mask */
0, /* dst_mask */
TRUE), /* pcrel_offset */
+
+ HOWTO (R_M32C_8, /* type */
+ 0, /* rightshift */
+ 0, /* size (0 = byte, 1 = short, 2 = long) */
+ 8, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_unsigned, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_M32C_8", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0x000000ff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ HOWTO (R_M32C_LO16, /* type */
+ 0, /* rightshift */
+ 1, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_M32C_LO16", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ HOWTO (R_M32C_HI8, /* type */
+ 0, /* rightshift */
+ 0, /* size (0 = byte, 1 = short, 2 = long) */
+ 8, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_M32C_HI8", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0x000000ff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ HOWTO (R_M32C_HI16, /* type */
+ 0, /* rightshift */
+ 1, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_M32C_HI16", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
};
/* Map BFD reloc types to M32C ELF reloc types. */
@@ -149,7 +205,11 @@ static const struct m32c_reloc_map m32c_
{ BFD_RELOC_24, R_M32C_24 },
{ BFD_RELOC_32, R_M32C_32 },
{ BFD_RELOC_8_PCREL, R_M32C_8_PCREL },
- { BFD_RELOC_16_PCREL, R_M32C_16_PCREL }
+ { BFD_RELOC_16_PCREL, R_M32C_16_PCREL },
+ { BFD_RELOC_8, R_M32C_8 },
+ { BFD_RELOC_LO16, R_M32C_LO16 },
+ { BFD_RELOC_HI16, R_M32C_HI16 },
+ { BFD_RELOC_M32C_HI8, R_M32C_HI8 }
};
static reloc_howto_type *
@@ -372,6 +432,11 @@ m32c_elf_relocate_section
}
}
break;
+
+ case R_M32C_HI8:
+ case R_M32C_HI16:
+ relocation >>= 16;
+ break;
}
r = _bfd_final_link_relocate (howto, input_bfd, input_section,
Index: bfd/reloc.c
===================================================================
RCS file: /cvs/src/src/bfd/reloc.c,v
retrieving revision 1.132
diff -p -U3 -r1.132 reloc.c
--- bfd/reloc.c 18 Jul 2005 14:13:36 -0000 1.132
+++ bfd/reloc.c 26 Jul 2005 02:22:48 -0000
@@ -3069,39 +3069,7 @@ ENUMDOC
DLX relocs
ENUM
- BFD_RELOC_M16C_8_PCREL8
-ENUMX
- BFD_RELOC_M16C_16_PCREL8
-ENUMX
- BFD_RELOC_M16C_8_PCREL16
-ENUMX
- BFD_RELOC_M16C_8_ELABEL24
-ENUMX
- BFD_RELOC_M16C_8_ABS16
-ENUMX
- BFD_RELOC_M16C_16_ABS16
-ENUMX
- BFD_RELOC_M16C_16_ABS24
-ENUMX
- BFD_RELOC_M16C_16_ABS32
-ENUMX
- BFD_RELOC_M16C_24_ABS16
-ENUMX
- BFD_RELOC_M16C_24_ABS24
-ENUMX
- BFD_RELOC_M16C_24_ABS32
-ENUMX
- BFD_RELOC_M16C_32_ABS16
-ENUMX
- BFD_RELOC_M16C_32_ABS24
-ENUMX
- BFD_RELOC_M16C_32_ABS32
-ENUMX
- BFD_RELOC_M16C_40_ABS16
-ENUMX
- BFD_RELOC_M16C_40_ABS24
-ENUMX
- BFD_RELOC_M16C_40_ABS32
+ BFD_RELOC_M32C_HI8
ENUMDOC
Renesas M16C/M32C Relocations.
Index: cpu/m32c.opc
===================================================================
RCS file: /cvs/src/src/cpu/m32c.opc,v
retrieving revision 1.4
diff -p -U3 -r1.4 m32c.opc
--- cpu/m32c.opc 18 Jul 2005 14:13:29 -0000 1.4
+++ cpu/m32c.opc 26 Jul 2005 02:22:48 -0000
@@ -153,6 +153,28 @@ parse_unsigned8 (CGEN_CPU_DESC cd, const
unsigned long value;
long have_zero = 0;
+ if (strncasecmp (*strp, "%dsp8(", 6) == 0)
+ {
+ enum cgen_parse_operand_result result_type;
+ bfd_vma value;
+ const char *errmsg;
+
+ *strp += 6;
+ errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_8,
+ & result_type, & value);
+ if (**strp != ')')
+ return _("missing `)'");
+ (*strp) ++;
+
+ if (errmsg == NULL
+ && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+ {
+ return _("%dsp8() takes a symbolic address, not a number");
+ }
+ *valuep = value;
+ return errmsg;
+ }
+
if (strncmp (*strp, "0x0", 3) == 0
|| (**strp == '0' && *(*strp + 1) != 'x'))
have_zero = 1;
@@ -201,7 +223,29 @@ parse_signed8 (CGEN_CPU_DESC cd, const c
{
const char *errmsg = 0;
signed long value;
-
+
+ if (strncasecmp (*strp, "%hi8(", 5) == 0)
+ {
+ enum cgen_parse_operand_result result_type;
+ bfd_vma value;
+ const char *errmsg;
+
+ *strp += 5;
+ errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32C_HI8,
+ & result_type, & value);
+ if (**strp != ')')
+ return _("missing `)'");
+ (*strp) ++;
+
+ if (errmsg == NULL
+ && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+ {
+ value >>= 16;
+ }
+ *valuep = value;
+ return errmsg;
+ }
+
PARSE_SIGNED;
if (value <= 255 && value > 127)
@@ -221,7 +265,29 @@ parse_unsigned16 (CGEN_CPU_DESC cd, cons
const char *errmsg = 0;
unsigned long value;
long have_zero = 0;
-
+
+ if (strncasecmp (*strp, "%dsp16(", 7) == 0)
+ {
+ enum cgen_parse_operand_result result_type;
+ bfd_vma value;
+ const char *errmsg;
+
+ *strp += 7;
+ errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_16,
+ & result_type, & value);
+ if (**strp != ')')
+ return _("missing `)'");
+ (*strp) ++;
+
+ if (errmsg == NULL
+ && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+ {
+ return _("%dsp16() takes a symbolic address, not a number");
+ }
+ *valuep = value;
+ return errmsg;
+ }
+
/* Don't successfully parse literals beginning with '['. */
if (**strp == '[')
return "Invalid literal"; /* Anything -- will not be seen. */
@@ -259,6 +325,50 @@ parse_signed16 (CGEN_CPU_DESC cd, const
const char *errmsg = 0;
signed long value;
+ if (strncasecmp (*strp, "%lo16(", 6) == 0)
+ {
+ enum cgen_parse_operand_result result_type;
+ bfd_vma value;
+ const char *errmsg;
+
+ *strp += 6;
+ errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_LO16,
+ & result_type, & value);
+ if (**strp != ')')
+ return _("missing `)'");
+ (*strp) ++;
+
+ if (errmsg == NULL
+ && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+ {
+ value &= 0xffff;
+ }
+ *valuep = value;
+ return errmsg;
+ }
+
+ if (strncasecmp (*strp, "%hi16(", 6) == 0)
+ {
+ enum cgen_parse_operand_result result_type;
+ bfd_vma value;
+ const char *errmsg;
+
+ *strp += 6;
+ errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_HI16,
+ & result_type, & value);
+ if (**strp != ')')
+ return _("missing `)'");
+ (*strp) ++;
+
+ if (errmsg == NULL
+ && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+ {
+ value >>= 16;
+ }
+ *valuep = value;
+ return errmsg;
+ }
+
PARSE_SIGNED;
if (value <= 65535 && value > 32767)
@@ -380,10 +490,10 @@ parse_lab_5_3 (CGEN_CPU_DESC cd,
int opindex ATTRIBUTE_UNUSED,
int opinfo,
enum cgen_parse_operand_result *type_addr,
- unsigned long *valuep)
+ bfd_vma *valuep)
{
const char *errmsg = 0;
- unsigned long value;
+ bfd_vma value;
enum cgen_parse_operand_result op_res;
errmsg = cgen_parse_address (cd, strp, M32C_OPERAND_LAB_5_3,
Index: gas/config/tc-m32c.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-m32c.c,v
retrieving revision 1.2
diff -p -U3 -r1.2 tc-m32c.c
--- gas/config/tc-m32c.c 18 Jul 2005 14:13:29 -0000 1.2
+++ gas/config/tc-m32c.c 26 Jul 2005 02:22:48 -0000
@@ -738,6 +738,27 @@ md_cgen_lookup_reloc (const CGEN_INSN *
int offset;
} op_reloc_table[] = {
+ /* Absolute relocs for 8-bit fields. */
+ { M32C_OPERAND_IMM_8_QI, BFD_RELOC_8, 1 },
+ { M32C_OPERAND_IMM_16_QI, BFD_RELOC_8, 2 },
+ { M32C_OPERAND_IMM_24_QI, BFD_RELOC_8, 3 },
+ { M32C_OPERAND_IMM_32_QI, BFD_RELOC_8, 4 },
+ { M32C_OPERAND_IMM_40_QI, BFD_RELOC_8, 5 },
+ { M32C_OPERAND_IMM_48_QI, BFD_RELOC_8, 6 },
+ { M32C_OPERAND_IMM_56_QI, BFD_RELOC_8, 7 },
+ { M32C_OPERAND_DSP_8_S8, BFD_RELOC_8, 1 },
+ { M32C_OPERAND_DSP_16_S8, BFD_RELOC_8, 2 },
+ { M32C_OPERAND_DSP_24_S8, BFD_RELOC_8, 3 },
+ { M32C_OPERAND_DSP_32_S8, BFD_RELOC_8, 4 },
+ { M32C_OPERAND_DSP_40_S8, BFD_RELOC_8, 5 },
+ { M32C_OPERAND_DSP_48_S8, BFD_RELOC_8, 6 },
+ { M32C_OPERAND_DSP_8_U8, BFD_RELOC_8, 1 },
+ { M32C_OPERAND_DSP_16_U8, BFD_RELOC_8, 2 },
+ { M32C_OPERAND_DSP_24_U8, BFD_RELOC_8, 3 },
+ { M32C_OPERAND_DSP_32_U8, BFD_RELOC_8, 4 },
+ { M32C_OPERAND_DSP_40_U8, BFD_RELOC_8, 5 },
+ { M32C_OPERAND_DSP_48_U8, BFD_RELOC_8, 6 },
+
/* Absolute relocs for 16-bit fields. */
{ M32C_OPERAND_IMM_16_HI, BFD_RELOC_16, 2 },
{ M32C_OPERAND_IMM_24_HI, BFD_RELOC_16, 3 },
@@ -777,6 +798,11 @@ md_cgen_lookup_reloc (const CGEN_INSN *
{
fixP->fx_where += or->offset;
fixP->fx_size -= or->offset;
+
+ if (fixP->fx_cgen.opinfo
+ && fixP->fx_cgen.opinfo != BFD_RELOC_NONE)
+ return fixP->fx_cgen.opinfo;
+
return or->reloc;
}
}
Index: gas/doc/c-m32c.texi
===================================================================
RCS file: /cvs/src/src/gas/doc/c-m32c.texi,v
retrieving revision 1.1
diff -p -U3 -r1.1 c-m32c.texi
--- gas/doc/c-m32c.texi 14 Jul 2005 22:52:09 -0000 1.1
+++ gas/doc/c-m32c.texi 26 Jul 2005 02:22:48 -0000
@@ -21,6 +21,7 @@ change the default to the M32C microproc
@menu
* M32C-Opts:: M32C Options
+* M32C-Modifiers:: Symbolic Operand Modifiers
@end menu
@node M32C-Opts
@@ -46,3 +47,70 @@ Assemble M32C instructions.
Assemble M16C instructions (default).
@end table
+
+@node M32C-Modifiers
+@section Symbolic Operand Modifiers
+
+@cindex M32C modifiers
+@cindex syntax, M32C
+
+The assembler supports several modifiers when using symbol addresses
+in M32C instruction operands. The general syntax is the following:
+
+@smallexample
+%modifier(symbol)
+@end smallexample
+
+@table @code
+@cindex symbol modifiers
+
+@item %dsp8
+@itemx %dsp16
+
+These modifiers override the assembler's assumptions about how big a
+symbol's address is. Normally, when it sees an operand like
+@samp{sym[a0]} it assumes @samp{sym} may require the widest
+displacement field (16 bits for @samp{-m16c}, 24 bits for
+@samp{-m32c}). These modifiers tell it to assume the address will fit
+in an 8 or 16 bit (respectively) unsigned displacement. Note that, of
+course, if it doesn't actually fit you will get linker errors. Example:
+
+@smallexample
+mov.w %dsp8(sym)[a0],r1
+mov.b #0,%dsp8(sym)[a0]
+@end smallexample
+
+@item %hi8
+
+This modifier allows you to load bits 16 through 23 of a 24 bit
+address into an 8 bit register. This is useful with, for example, the
+M16C @samp{smovf} instruction, which expects a 20 bit address in
+@samp{r1h} and @samp{a0}. Example:
+
+@smallexample
+mov.b #%hi8(sym),r1h
+mov.w #%lo16(sym),a0
+smovf.b
+@end smallexample
+
+@item %lo16
+
+Likewise, this modifier allows you to load bits 0 through 15 of a 24
+bit address into a 16 bit register.
+
+@item %hi16
+
+This modifier allows you to load bits 16 through 31 of a 32 bit
+address into a 16 bit register. While the M32C family only has 24
+bits of address space, it does support addresses in pairs of 16 bit
+registers (like @samp{a1a0} for the @samp{lde} instruction). This
+modifier is for loading the upper half in such cases. Example:
+
+@smallexample
+mov.w #%hi16(sym),a1
+mov.w #%lo16(sym),a0
+@dots{}
+lde.w [a1a0],r1
+@end smallexample
+
+@end table
Index: include/elf/m32c.h
===================================================================
RCS file: /cvs/src/src/include/elf/m32c.h,v
retrieving revision 1.1
diff -p -U3 -r1.1 m32c.h
--- include/elf/m32c.h 14 Jul 2005 22:52:15 -0000 1.1
+++ include/elf/m32c.h 26 Jul 2005 02:22:49 -0000
@@ -30,6 +30,16 @@ along with this program; if not, write t
RELOC_NUMBER (R_M32C_32, 3)
RELOC_NUMBER (R_M32C_8_PCREL, 4)
RELOC_NUMBER (R_M32C_16_PCREL, 5)
+
+ /* 8 bit unsigned address, used for dsp8[a0] etc */
+ RELOC_NUMBER (R_M32C_8, 6)
+ /* Bits 0..15 of an address, for SMOVF's A0, A1A0, etc. */
+ RELOC_NUMBER (R_M32C_LO16, 7)
+ /* Bits 16..23 of an address, for SMOVF's R1H etc. */
+ RELOC_NUMBER (R_M32C_HI8, 8)
+ /* Bits 16..31 of an address, for LDE's A1A0 etc. */
+ RELOC_NUMBER (R_M32C_HI16, 9)
+
END_RELOC_NUMBERS (R_M32C_max)
#define EF_M32C_CPU_M16C 0x00000075 /* default */
Index: opcodes/m32c-asm.c
===================================================================
RCS file: /cvs/src/src/opcodes/m32c-asm.c,v
retrieving revision 1.2
diff -p -U3 -r1.2 m32c-asm.c
--- opcodes/m32c-asm.c 18 Jul 2005 14:13:29 -0000 1.2
+++ opcodes/m32c-asm.c 26 Jul 2005 02:22:49 -0000
@@ -127,6 +127,28 @@ parse_unsigned8 (CGEN_CPU_DESC cd, const
unsigned long value;
long have_zero = 0;
+ if (strncasecmp (*strp, "%dsp8(", 6) == 0)
+ {
+ enum cgen_parse_operand_result result_type;
+ bfd_vma value;
+ const char *errmsg;
+
+ *strp += 6;
+ errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_8,
+ & result_type, & value);
+ if (**strp != ')')
+ return _("missing `)'");
+ (*strp) ++;
+
+ if (errmsg == NULL
+ && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+ {
+ return _("%dsp8() takes a symbolic address, not a number");
+ }
+ *valuep = value;
+ return errmsg;
+ }
+
if (strncmp (*strp, "0x0", 3) == 0
|| (**strp == '0' && *(*strp + 1) != 'x'))
have_zero = 1;
@@ -175,7 +197,29 @@ parse_signed8 (CGEN_CPU_DESC cd, const c
{
const char *errmsg = 0;
signed long value;
-
+
+ if (strncasecmp (*strp, "%hi8(", 5) == 0)
+ {
+ enum cgen_parse_operand_result result_type;
+ bfd_vma value;
+ const char *errmsg;
+
+ *strp += 5;
+ errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32C_HI8,
+ & result_type, & value);
+ if (**strp != ')')
+ return _("missing `)'");
+ (*strp) ++;
+
+ if (errmsg == NULL
+ && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+ {
+ value >>= 16;
+ }
+ *valuep = value;
+ return errmsg;
+ }
+
PARSE_SIGNED;
if (value <= 255 && value > 127)
@@ -195,7 +239,29 @@ parse_unsigned16 (CGEN_CPU_DESC cd, cons
const char *errmsg = 0;
unsigned long value;
long have_zero = 0;
-
+
+ if (strncasecmp (*strp, "%dsp16(", 7) == 0)
+ {
+ enum cgen_parse_operand_result result_type;
+ bfd_vma value;
+ const char *errmsg;
+
+ *strp += 7;
+ errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_16,
+ & result_type, & value);
+ if (**strp != ')')
+ return _("missing `)'");
+ (*strp) ++;
+
+ if (errmsg == NULL
+ && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+ {
+ return _("%dsp16() takes a symbolic address, not a number");
+ }
+ *valuep = value;
+ return errmsg;
+ }
+
/* Don't successfully parse literals beginning with '['. */
if (**strp == '[')
return "Invalid literal"; /* Anything -- will not be seen. */
@@ -233,6 +299,50 @@ parse_signed16 (CGEN_CPU_DESC cd, const
const char *errmsg = 0;
signed long value;
+ if (strncasecmp (*strp, "%lo16(", 6) == 0)
+ {
+ enum cgen_parse_operand_result result_type;
+ bfd_vma value;
+ const char *errmsg;
+
+ *strp += 6;
+ errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_LO16,
+ & result_type, & value);
+ if (**strp != ')')
+ return _("missing `)'");
+ (*strp) ++;
+
+ if (errmsg == NULL
+ && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+ {
+ value &= 0xffff;
+ }
+ *valuep = value;
+ return errmsg;
+ }
+
+ if (strncasecmp (*strp, "%hi16(", 6) == 0)
+ {
+ enum cgen_parse_operand_result result_type;
+ bfd_vma value;
+ const char *errmsg;
+
+ *strp += 6;
+ errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_HI16,
+ & result_type, & value);
+ if (**strp != ')')
+ return _("missing `)'");
+ (*strp) ++;
+
+ if (errmsg == NULL
+ && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+ {
+ value >>= 16;
+ }
+ *valuep = value;
+ return errmsg;
+ }
+
PARSE_SIGNED;
if (value <= 65535 && value > 32767)
@@ -354,10 +464,10 @@ parse_lab_5_3 (CGEN_CPU_DESC cd,
int opindex ATTRIBUTE_UNUSED,
int opinfo,
enum cgen_parse_operand_result *type_addr,
- unsigned long *valuep)
+ bfd_vma *valuep)
{
const char *errmsg = 0;
- unsigned long value;
+ bfd_vma value;
enum cgen_parse_operand_result op_res;
errmsg = cgen_parse_address (cd, strp, M32C_OPERAND_LAB_5_3,
Index: opcodes/m32c-dis.c
===================================================================
RCS file: /cvs/src/src/opcodes/m32c-dis.c,v
retrieving revision 1.2
diff -p -U3 -r1.2 m32c-dis.c
--- opcodes/m32c-dis.c 18 Jul 2005 14:13:31 -0000 1.2
+++ opcodes/m32c-dis.c 26 Jul 2005 02:22:49 -0000
@@ -1229,7 +1229,7 @@ print_insn_m32c (bfd_vma pc, disassemble
break;
}
}
- }
+ }
/* If we haven't initialized yet, initialize the opcode table. */
if (! cd)