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Re: [PATCH] arm: fadds instruction is disassembled incorrectly byobjdump
- From: Nick Clifton <nickc at redhat dot com>
- To: Khem Raj <kraj at mvista dot com>
- Cc: binutils at sourceware dot org
- Date: Thu, 07 Jul 2005 12:43:09 +0100
- Subject: Re: [PATCH] arm: fadds instruction is disassembled incorrectly byobjdump
- References: <42CC643C.3080308@mvista.com>
Hi Khem,
2005-07-06 Khem Raj <kraj@mvista.com>
* arm-dis.c (opcode32 arm_opcodes): Fix ARM VFP fadds instruction
disassembly pattern.
Approved and applied.
Thanks for finding and fixing this bug.
Note - I have also applied a patch to the GAS testsuite which was
expecting the old (wrong) disassembly.
Cheers
Nick
gas/testsuite/ChangeLog
2005-07-07 Nick Clifton <nickc@redhat.com>
* gas/arm/vfp1xD.d: Adjust expected fadds disassembles now that
the disassembler has been fixed.
Index: gas/testsuite/gas/arm/vfp1xD.d
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/arm/vfp1xD.d,v
retrieving revision 1.3
diff -c -3 -p -r1.3 vfp1xD.d
*** gas/testsuite/gas/arm/vfp1xD.d 3 Nov 2003 14:47:37 -0000 1.3
--- gas/testsuite/gas/arm/vfp1xD.d 7 Jul 2005 11:36:34 -0000
*************** Disassembly of section .text:
*** 82,97 ****
0+120 <[^>]*> eeb11a40 fnegs s2, s0
0+124 <[^>]*> eef1fa40 fnegs s31, s0
0+128 <[^>]*> eeb16a6a fnegs s12, s21
! 0+12c <[^>]*> ee300a20 fadds s0, s0, s0
! 0+130 <[^>]*> ee300a01 fadds s0, s0, s0
! 0+134 <[^>]*> ee300a2f fadds s0, s0, s0
0+138 <[^>]*> ee300a80 fadds s0, s1, s0
0+13c <[^>]*> ee310a00 fadds s0, s2, s0
0+140 <[^>]*> ee3f0a80 fadds s0, s31, s0
! 0+144 <[^>]*> ee700a00 fadds s1, s0, s1
! 0+148 <[^>]*> ee301a00 fadds s2, s0, s2
! 0+14c <[^>]*> ee70fa00 fadds s31, s0, s31
! 0+150 <[^>]*> ee3a6aa2 fadds s12, s21, s12
0+154 <[^>]*> eeb80ae0 fsitos s0, s1
0+158 <[^>]*> eeb80ac1 fsitos s0, s2
0+15c <[^>]*> eeb80aef fsitos s0, s31
--- 82,97 ----
0+120 <[^>]*> eeb11a40 fnegs s2, s0
0+124 <[^>]*> eef1fa40 fnegs s31, s0
0+128 <[^>]*> eeb16a6a fnegs s12, s21
! 0+12c <[^>]*> ee300a20 fadds s0, s0, s1
! 0+130 <[^>]*> ee300a01 fadds s0, s0, s2
! 0+134 <[^>]*> ee300a2f fadds s0, s0, s31
0+138 <[^>]*> ee300a80 fadds s0, s1, s0
0+13c <[^>]*> ee310a00 fadds s0, s2, s0
0+140 <[^>]*> ee3f0a80 fadds s0, s31, s0
! 0+144 <[^>]*> ee700a00 fadds s1, s0, s0
! 0+148 <[^>]*> ee301a00 fadds s2, s0, s0
! 0+14c <[^>]*> ee70fa00 fadds s31, s0, s0
! 0+150 <[^>]*> ee3a6aa2 fadds s12, s21, s5
0+154 <[^>]*> eeb80ae0 fsitos s0, s1
0+158 <[^>]*> eeb80ac1 fsitos s0, s2
0+15c <[^>]*> eeb80aef fsitos s0, s31
*************** Disassembly of section .text:
*** 194,200 ****
0+2e0 <[^>]*> 0ef0fa69 fcpyseq s31, s19
0+2e4 <[^>]*> 0eb1aa44 fnegseq s20, s8
0+2e8 <[^>]*> 0ef12ae3 fsqrtseq s5, s7
! 0+2ec <[^>]*> 0e323a82 faddseq s6, s5, s6
0+2f0 <[^>]*> 0ec11a20 fdivseq s3, s2, s1
0+2f4 <[^>]*> 0e4ffa2e fmacseq s31, s30, s29
0+2f8 <[^>]*> 0e1dea8d fmscseq s28, s27, s26
--- 194,200 ----
0+2e0 <[^>]*> 0ef0fa69 fcpyseq s31, s19
0+2e4 <[^>]*> 0eb1aa44 fnegseq s20, s8
0+2e8 <[^>]*> 0ef12ae3 fsqrtseq s5, s7
! 0+2ec <[^>]*> 0e323a82 faddseq s6, s5, s4
0+2f0 <[^>]*> 0ec11a20 fdivseq s3, s2, s1
0+2f4 <[^>]*> 0e4ffa2e fmacseq s31, s30, s29
0+2f8 <[^>]*> 0e1dea8d fmscseq s28, s27, s26