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Re: ARMv6T2 ARM instructions - assembler support


On Mon, 2005-03-14 at 23:21, Zack Weinberg wrote:
> This patch adds assembler support for the new ARM-format instructions
> in ARMv6T2, and tests for them (and hence also for the disassembler
> patch I committed last week).
> 
> zw
> 
> gas:
>         * config/tc-arm.c (do_mla): Rename to do_mlas, take second
>         is_mls parameter.
>         (do_mla, do_mls, five_bit_unsigned_immediate, bfci_lsb_and_width)
>         (do_bfc, do_bfi, do_bfx, do_rbit, do_mov16, do_ldsttv4): New functions.
>         (insns): Add ARMv6T2 instructions:
>         bfc bfi mls movw movt rbit sbfx ubfx ldrht ldrsht ldrsbt strht.
>         (arm_archs): Add V6T2 variants.
> gas/testsuite:
>         * gas/arm/archv6t2.d, gas/arm/archv6t2.s: New dump test.
>         * gas/arm/archv6t2-bad.l, gas/arm/archv6t2-bad.l: New errors test.
>         * gas/arm/arm.exp: Run them.
>  
> @@ -2847,7 +2847,12 @@ do_mla (char * str)
>      }
>  
>    if (rm == rd)
> -    as_tsktsk (_("rd and rm should be different in mla"));
> +    {
> +      if (is_mls)
> +	as_tsktsk (_("rd and rm should be different in mls"));
> +      else
> +	as_tsktsk (_("rd and rm should be different in mla"));
> +    }
>  

mls doesn't have this restriction.  v6 lifted the restriction for mla
too, and in practice all v4 or later cores don't have it either, but
that's hard to fix with the current -mcpu=all implementation.

OK apart from that.

R.

PS.

Just a note on the way I normally write tests.  For each class of
instruction (a do_xxx function) I try to write a test pattern that sets
the minimal number of bits in the insn (eg uses r0 everywhere possible)
and then one pattern for each register (to check that each register is
setting the right bits).  Finally, if the instruction is conditional, at
least one pattern should test this case.



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