Re: how to calculate opcode mask

[Shinpei Kato <shinny at j02 dot itscom dot net>]

Thank you for your replying.

> The mask picks out the fixed bits in the instruction.  Any instruction
> for which
>     (insn & 0xfc0007ff) == 0x20
> is the add instruction.
> 
> The assembler does not use the mask field in any significant way.  It
> is the disassembler which uses the mask field.  It uses it to decide
> which instruction it is looking at.
> 
> 0xfc0007ff is closely related to "d,v,t", because the assembler will
> use those codes to fill in the bits which are zero in 0xfc0007ff.  The
> letter codes are defined in include/opcode/mips.h.  But I don't think
> there is a one-to-one mapping between letter codes and the mask.

I see. I couldn't get it by myself. But I need the mask after all, don't
I? Sorry for my weak brain, I can't still understand how I can set up
the mask.
I don't think I can't find answer 0xfc0007ff with macros in
include/opcode/mips.h, though... How can I?

And could I ask one more question?
There are several shift counters for registers such as OP_SH_FT,
OP_SH_FS, etc. Maybe these are used to set up a next register number, I
suppose. 
Then, how these shift counters are decided? If I want to change the
number of the registers, for example changing the floating-point regs
number to 8 from 32, do I have to change the shift counters? If so, how
do I do it?
Please forgive my asking after asking. I'm a newbie to GCC & Binutils.
:-)

I appreciate your help.

Regards,
Shinpei Kato.