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[patch] *-h8300.c: Add and adjust more comments about relaxation.
- From: Kazu Hirata <kazu at cs dot umass dot edu>
- To: binutils at sources dot redhat dot com
- Cc: anilp1 at KPITCummins dot com
- Date: Mon, 19 Jan 2004 12:09:30 -0500 (EST)
- Subject: [patch] *-h8300.c: Add and adjust more comments about relaxation.
Hi,
Attached is a patch to add and adjust more comments about relaxation.
In personal communication, Anil Paranjpe pointed out to me that
R_H8_DIR32A16 in elf32-h8300.c and R_MOVL2 in coff-h8300.c do more
relaxation than described in the comment. Look for "32-bit" in the
patch for comments in this area.
The rest of the patch is simply clarification.
Committed as obvious.
Kazu Hirata
2004-01-19 Kazu Hirata <kazu@cs.umass.edu>
* coff-h8300.c: Add and adjust comments about relaxation.
* elf32-h8300.c: Likewise.
Index: coff-h8300.c
===================================================================
RCS file: /cvs/src/src/bfd/coff-h8300.c,v
retrieving revision 1.28
diff -c -r1.28 coff-h8300.c
*** coff-h8300.c 16 Jan 2004 23:50:19 -0000 1.28
--- coff-h8300.c 19 Jan 2004 16:59:26 -0000
***************
*** 776,783 ****
src_address += 4;
break;
! /* A 16-bit absolute relocation that was formerly a 24-/32-bit
! absolute relocation. */
case R_MOVL2:
value = bfd_coff_reloc16_get_value (reloc, link_info, input_section);
value = bfd_h8300_pad_address (abfd, value);
--- 776,790 ----
src_address += 4;
break;
! /* This is a 24-/32-bit absolute address in one of the following
! instructions:
!
! "band", "bclr", "biand", "bild", "bior", "bist", "bixor",
! "bld", "bnot", "bor", "bset", "bst", "btst", "bxor", and
! "mov.[bwl]"
!
! We may relax this into an 16-bit absolute address if it's in
! the right range. */
case R_MOVL2:
value = bfd_coff_reloc16_get_value (reloc, link_info, input_section);
value = bfd_h8300_pad_address (abfd, value);
***************
*** 788,795 ****
/* Insert the 16-bit value into the proper location. */
bfd_put_16 (abfd, value, data + dst_address);
! /* Fix the opcode. For all the move insns, we simply
! need to turn off bit 0x20 in the previous byte. */
data[dst_address - 1] &= ~0x20;
dst_address += 2;
src_address += 4;
--- 795,803 ----
/* Insert the 16-bit value into the proper location. */
bfd_put_16 (abfd, value, data + dst_address);
! /* Fix the opcode. For all the instructions that belong to
! this relaxation, we simply need to turn off bit 0x20 in
! the previous byte. */
data[dst_address - 1] &= ~0x20;
dst_address += 2;
src_address += 4;
***************
*** 834,840 ****
bfd_put_8 (abfd, 0x55, data + dst_address - 1);
break;
case 0x5a:
! /* jmp ->bra */
bfd_put_8 (abfd, 0x40, data + dst_address - 1);
break;
--- 842,848 ----
bfd_put_8 (abfd, 0x55, data + dst_address - 1);
break;
case 0x5a:
! /* jmp -> bra */
bfd_put_8 (abfd, 0x40, data + dst_address - 1);
break;
***************
*** 877,888 ****
{
case 0x58:
/* bCC:16 -> bCC:8 */
! /* Get the condition code from the original insn. */
tmp = data[dst_address - 1];
tmp &= 0xf0;
tmp >>= 4;
-
- /* Now or in the high nibble of the opcode. */
tmp |= 0x40;
/* Write it. */
--- 885,899 ----
{
case 0x58:
/* bCC:16 -> bCC:8 */
! /* Get the second byte of the original insn, which contains
! the condition code. */
tmp = data[dst_address - 1];
+
+ /* Compute the fisrt byte of the relaxed instruction. The
+ original sequence 0x58 0xX0 is relaxed to 0x4X, where X
+ represents the condition code. */
tmp &= 0xf0;
tmp >>= 4;
tmp |= 0x40;
/* Write it. */
Index: elf32-h8300.c
===================================================================
RCS file: /cvs/src/src/bfd/elf32-h8300.c,v
retrieving revision 1.39
diff -c -r1.39 elf32-h8300.c
*** elf32-h8300.c 16 Jan 2004 23:50:20 -0000 1.39
--- elf32-h8300.c 19 Jan 2004 16:59:28 -0000
***************
*** 666,671 ****
--- 666,674 ----
mov.b:16 -> mov.b:8 2 bytes
mov.b:24/32 -> mov.b:8 4 bytes
+ bset:24/32 -> bset:16 2 bytes
+ (also applicable to other bit manipulation instructions)
+
mov.[bwl]:24/32 -> mov.[bwl]:16 2 bytes */
static bfd_boolean
***************
*** 919,926 ****
--- 922,931 ----
}
if (code == 0x5e)
+ /* This is jsr. */
bfd_put_8 (abfd, 0x55, contents + irel->r_offset - 1);
else if (code == 0x5a)
+ /* This is jmp. */
bfd_put_8 (abfd, 0x40, contents + irel->r_offset - 1);
else
abort ();
***************
*** 975,988 ****
if (code == 0x58)
{
/* bCC:16 -> bCC:8 */
! /* Get the condition code from the original insn. */
code = bfd_get_8 (abfd, contents + irel->r_offset - 1);
code &= 0xf0;
code >>= 4;
code |= 0x40;
bfd_put_8 (abfd, code, contents + irel->r_offset - 2);
}
else if (code == 0x5c)
bfd_put_8 (abfd, 0x55, contents + irel->r_offset - 2);
else
abort ();
--- 980,1000 ----
if (code == 0x58)
{
/* bCC:16 -> bCC:8 */
! /* Get the second byte of the original insn, which
! contains the condition code. */
code = bfd_get_8 (abfd, contents + irel->r_offset - 1);
+
+ /* Compute the fisrt byte of the relaxed
+ instruction. The original sequence 0x58 0xX0
+ is relaxed to 0x4X, where X represents the
+ condition code. */
code &= 0xf0;
code >>= 4;
code |= 0x40;
bfd_put_8 (abfd, code, contents + irel->r_offset - 2);
}
else if (code == 0x5c)
+ /* This is bsr. */
bfd_put_8 (abfd, 0x55, contents + irel->r_offset - 2);
else
abort ();
***************
*** 1179,1189 ****
}
}
! /* Fall through. */
! /* This is a 24-/32-bit absolute address in a "mov" insn,
! which may become a 16-bit absolute address if it is in the
! right range. */
case R_H8_DIR32A16:
{
bfd_vma value;
--- 1191,1207 ----
}
}
! /* Fall through. */
!
! /* This is a 24-/32-bit absolute address in one of the
! following instructions:
!
! "band", "bclr", "biand", "bild", "bior", "bist",
! "bixor", "bld", "bnot", "bor", "bset", "bst", "btst",
! "bxor", and "mov.[bwl]"
! We may relax this into an 16-bit absolute address if it's
! in the right range. */
case R_H8_DIR32A16:
{
bfd_vma value;
***************
*** 1202,1208 ****
/* Get the opcode. */
code = bfd_get_8 (abfd, contents + irel->r_offset - 1);
! /* We just need to turn off bit 0x20. */
code &= ~0x20;
bfd_put_8 (abfd, code, contents + irel->r_offset - 1);
--- 1220,1228 ----
/* Get the opcode. */
code = bfd_get_8 (abfd, contents + irel->r_offset - 1);
! /* Fix the opcode. For all the instructions that
! belong to this relaxation, we simply need to turn
! off bit 0x20 in the previous byte. */
code &= ~0x20;
bfd_put_8 (abfd, code, contents + irel->r_offset - 1);