Gas patch for reading alternate forms of MIPS coprocessor registernames, take 2

[Matt Hiller <hiller at redhat dot com>]

This now includes:

* A check that the proper coprocessor number is referenced in the regname.

* A run_test_dump test and a run_test_list test that checks to see that 
proper errors are generated.

* Code for processing $c1rNN names if they appear in regular fp 
instructions (this is also tested in the run_test_dump test).

The new tests pass and there are no regressions -- okay to apply?

2002-06-20  Matt Hiller  <hiller@redhat.com>

	* config/tc-mips.c (mips_ip): Process $cKrNN register names.

	* testsuite/gas/mips/illegal-cop.s: New testcase.
	* testsuite/gas/mips/illegal-cop.l: Listing output for above.
	* testsuite/gas/mips/mipscops.s: New testcase.
	* testsuite/gas/mips/mipscops.d: Dump output for above.
	* testsuite/gas/mips/mips.exp: Invoke above tests.

Index: config/tc-mips.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-mips.c,v
retrieving revision 1.119
diff -u -p -r1.119 tc-mips.c
--- config/tc-mips.c	4 May 2002 17:38:00 -0000	1.119
+++ config/tc-mips.c	20 Jun 2002 19:51:00 -0000
@@ -7641,6 +7641,7 @@ mips_ip (str, ip)
   unsigned int lastregno = 0;
   char *s_reset;
   char save_c = 0;
+  unsigned int valid_fp_regname;
 
   insn_error = NULL;
 
@@ -7937,6 +7938,24 @@ mips_ip (str, ip)
 	      if (s[0] == '$')
 		{
 
+		  /* Allow '$cKrNN" as a coprocessor register name.
+		     Check to be sure that the register name is
+		     appropriate for the instruction, too.
+
+		     For example, "mfc0 $2,$c3r12" wouldn't be valid.  */
+
+		  if ((*args == 'E' || *args == 'G') && s[1] == 'c'
+		      && (s[2] == '0' || s[2] == '1' || s[2] == '2'
+			  || s[2] == '3')
+		      && s[3] == 'r')
+		    {
+		      static char needle[] = "c_";
+
+		      needle[1] = s[2];
+		      if (!strstr (insn->name, needle))
+			insn_error = _("illegal coprocessor operand");
+		      s += 3;
+		    }
 		  if (ISDIGIT (s[1]))
 		    {
 		      ++s;
@@ -8100,10 +8119,21 @@ mips_ip (str, ip)
 	    case 'V':
 	    case 'W':
 	      s_reset = s;
+	      valid_fp_regname = 0;
 	      if (s[0] == '$' && s[1] == 'f'
 		  && ISDIGIT (s[2]))
 		{
 		  s += 2;
+		  valid_fp_regname = 1;
+		}
+	      else if (s[0] == '$' && s[1] == 'c' && s[2] == '1'
+		       && s[3] == 'r' && ISDIGIT (s[4]))
+		{
+		  s += 4;
+		  valid_fp_regname = 1;
+		}
+	      if (valid_fp_regname)
+		{
 		  regno = 0;
 		  do
 		    {
Index: testsuite/gas/mips/illegal-cop.l
===================================================================
RCS file: testsuite/gas/mips/illegal-cop.l
diff -N testsuite/gas/mips/illegal-cop.l
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ testsuite/gas/mips/illegal-cop.l	20 Jun 2002 19:51:00 -0000
@@ -0,0 +1,6 @@
+.*: Assembler messages:
+.*:4: Error: illegal coprocessor operand `mfc2'
+.*:5: Error: illegal coprocessor operand `mtc1'
+.*:6: Error: illegal operands `lwc2 \$f13,0\(\$fp\)'
+.*:7: Error: illegal coprocessor operand `swc3'
+.*:8: Error: Invalid register number \(40\)
\ No newline at end of file
Index: testsuite/gas/mips/illegal-cop.s
===================================================================
RCS file: testsuite/gas/mips/illegal-cop.s
diff -N testsuite/gas/mips/illegal-cop.s
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ testsuite/gas/mips/illegal-cop.s	20 Jun 2002 19:51:01 -0000
@@ -0,0 +1,9 @@
+# Source file used to test illegal coprocessor operands.
+	
+foo:
+	mfc2 $4,$c0r4
+	mtc1 $4,$c0r4
+	lwc2 $f13,0($fp)
+	swc3 $c2r20,b
+	mfc2 $2,$c2r40
+	
\ No newline at end of file
Index: testsuite/gas/mips/mips.exp
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/mips/mips.exp,v
retrieving revision 1.32
diff -u -p -r1.32 mips.exp
--- testsuite/gas/mips/mips.exp	4 Apr 2002 08:23:30 -0000	1.32
+++ testsuite/gas/mips/mips.exp	20 Jun 2002 19:51:01 -0000
@@ -158,6 +158,7 @@ if { [istarget mips*-*-*] } then {
     run_dump_test "relax"
 
     run_list_test "illegal" ""
+    run_list_test "illegal-cop" ""
 
     # LOSE: As of 2002-02-08, the next 4 tests fail for target mips-ecoff.
     # It's unknown whether they _should_ pass as-is, or whether different
@@ -166,6 +167,7 @@ if { [istarget mips*-*-*] } then {
     run_dump_test "mips-gp32-fp64"
     run_dump_test "mips-gp64-fp32"
     run_dump_test "mips-gp64-fp64"
+    run_dump_test "mipscops"
 
     if $elf {
 	# Make sure that -mcpu=FOO and -mFOO are equivalent.  Assemble a file
Index: testsuite/gas/mips/mipscops.d
===================================================================
RCS file: testsuite/gas/mips/mipscops.d
diff -N testsuite/gas/mips/mipscops.d
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ testsuite/gas/mips/mipscops.d	20 Jun 2002 19:51:01 -0000
@@ -0,0 +1,30 @@
+# objdump: -dr --prefix-addresses -mmips:3000
+# name: MIPS coprocessors
+# as: -mips1
+
+# Test the assembly of coprocessor register names
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+[0-9a-f]+ <[^>]*> mfc0	zero,\$0
+[0-9a-f]+ <[^>]*> mfc0	v0,\$1
+[0-9a-f]+ <[^>]*> mtc1	v1,\$f0
+[0-9a-f]+ <[^>]*> mtc1	a0,\$f1
+[0-9a-f]+ <[^>]*> mtc1	a1,\$f2
+[0-9a-f]+ <[^>]*> mfc2	a2,\$0
+[0-9a-f]+ <[^>]*> mfc2	a3,\$1
+[0-9a-f]+ <[^>]*> mtc3	t0,\$0
+[0-9a-f]+ <[^>]*> nop
+[0-9a-f]+ <[^>]*> mtc3	t1,\$1
+[0-9a-f]+ <[^>]*> nop
+[0-9a-f]+ <[^>]*> swc0	\$2,0\(s8\)
+[0-9a-f]+ <[^>]*> swc0	\$3,4\(s8\)
+[0-9a-f]+ <[^>]*> lwc1	\$f3,8\(s8\)
+[0-9a-f]+ <[^>]*> lwc1	\$f4,12\(s8\)
+[0-9a-f]+ <[^>]*> lwc1	\$f5,16\(s8\)
+[0-9a-f]+ <[^>]*> swc2	\$2,20\(s8\)
+[0-9a-f]+ <[^>]*> swc2	\$3,24\(s8\)
+[0-9a-f]+ <[^>]*> lwc3	\$2,28\(s8\)
+[0-9a-f]+ <[^>]*> lwc3	\$3,32\(s8\)
+[0-9a-f]+ <[^>]*> c.f.s	\$f6,\$f8
Index: testsuite/gas/mips/mipscops.s
===================================================================
RCS file: testsuite/gas/mips/mipscops.s
diff -N testsuite/gas/mips/mipscops.s
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ testsuite/gas/mips/mipscops.s	20 Jun 2002 19:51:01 -0000
@@ -0,0 +1,25 @@
+# Source file used to test that the assembler handles all forms of coprocessor
+# operands
+
+foo:
+	mfc0 $0,$0
+	mfc0 $2,$c0r1
+	mtc1 $3,$0
+	mtc1 $4,$c1r1
+	mtc1 $5,$f2
+	mfc2 $6,$0
+	mfc2 $7,$c2r1
+	mtc3 $8,$0
+	mtc3 $9,$c3r1
+
+	swc0 $2,0($fp)
+	swc0 $c0r3,4($fp)
+	lwc1 $3,8($fp)
+	lwc1 $c1r4,12($fp)
+	lwc1 $f5,16($fp)
+	swc2 $2,20($fp)
+	swc2 $c2r3,24($fp)
+	lwc3 $2,28($fp)
+	lwc3 $c3r3,32($fp)
+	
+	c.f.s $c1r6,$c1r8