This is the mail archive of the
binutils@sources.redhat.com
mailing list for the binutils project.
binutils patches for Cirrus/arm9e/maverick support
- To: binutils at sources dot redhat dot com
- Subject: binutils patches for Cirrus/arm9e/maverick support
- From: Aldy Hernandez <aldyh at redhat dot com>
- Date: 08 Oct 2001 13:34:43 -0400
- Cc: Nick Clifton <nickc at cygnus dot com>
hi guys!
i've been sitting on this long enough. it's about time i contribute it.
the following are patches for gas, ld, opcodes, and bfd-- for the Cirrus
DSP arm copprocessor (arm9e).
we have had these patches integrated and working (on our tree) for the
past year and a half, and they're pretty much cookie cutter stuff.
more patches to follow, but i want to get the binutils part out of the
way.
all code here is mine, so you can blame me. except that maverick.c test
generator. that's alex oliva's baby.
ok to install?
--
Aldy Hernandez E-mail: aldyh@redhat.com
Professional Gypsy on a [broken] Motorcycle
Red Hat, Inc.
2001-10-08 Aldy Hernandez <aldyh@redhat.com>
* opcodess/arm-opc.h (arm_opcodes): Add cirrus insns.
* opcodes/arm-dis.c (print_insn_arm): Add 'I' case.
* ld/configure.tgt (targ): Add arm9e-*-elf.
* gas/testsuite/gas/arm/arm.exp: Run arm9e tests.
* gas/testsuite/gas/arm/maverick.c: New.
* gas/testsuite/gas/arm/maverick.d: New.
* gas/testsuite/gas/arm/maverick.s: New.
* gas/doc/arm/c-arm.texi (ARM Options): Add arm9e documentation.
* gas/config/tc-arm.c (ARM_EXT_MAVERIK): New macro.
(cirrus_regtype): New enum.
(LONGEST_INST): Change to 10.
(CIRRUS_MODE1): New.
(CIRRUS_MODE2): New.
(CIRRUS_MODE3): New.
(CIRRUS_MODE4): New.
(CIRRUS_MODE5): New.
(CIRRUS_MODE6): New.
(insns): Add cirrus dsp instructions.
(ARM_EXT_MAVERIKSC_REG): New.
(cirrus_register): New.
(cirrus_mvf_register): New.
(cirrus_mvd_register): New.
(cirrus_mvfx_register): New.
(cirrus_mvdx_register): New.
(cirrus_mvax_register): New.
(ARM_EXT_MAVERIKsc_register): New.
(reg_table): Add cirrus registers.
(cirrus_valid_reg): New.
(cirrus_reg_required_here): New.
(do_c_binops_1): New.
(do_c_binops_2): New.
(do_c_binops_3): New.
(do_c_triple_4): New.
(do_c_triple_5): New.
(do_c_quad_6): New.
(do_c_dspsc_1): New.
(do_c_dspsc_2): New.
(do_c_shift_1): New.
(do_c_shift_2): New.
(do_c_ldst_1): New.
(do_c_ldst_2): New.
(do_c_ldst_3): New.
(do_c_ldst_4): New.
(do_c_binops): New.
(do_c_triple): New.
(do_c_quad): New.
(do_c_dspsc): New.
(do_c_shift): New.
(cirrus_parse_offset): New.
(do_c_ldst): New.
(md_parse_option): Add arm9e.
(md_show_usage): Same.
* bfd/config.bfd (targ_cpu): Add arm9e-*-elf.
Index: bfd/config.bfd
===================================================================
RCS file: /cvs/uberbaum/bfd/config.bfd,v
retrieving revision 1.68
diff -c -p -r1.68 config.bfd
*** config.bfd 2001/09/14 11:46:39 1.68
--- config.bfd 2001/10/08 17:22:58
*************** case "${targ}" in
*** 167,172 ****
--- 167,176 ----
targ_defvec=bfd_elf32_littlearm_vec
targ_selvecs=bfd_elf32_bigarm_vec
;;
+ arm9e-*-elf)
+ targ_defvec=bfd_elf32_littlearm_vec
+ targ_selvecs=bfd_elf32_bigarm_vec
+ ;;
arm-*-oabi)
targ_defvec=bfd_elf32_littlearm_oabi_vec
targ_selvecs=bfd_elf32_bigarm_oabi_vec
Index: gas/config/tc-arm.c
===================================================================
RCS file: /cvs/uberbaum/gas/config/tc-arm.c,v
retrieving revision 1.92
diff -c -p -r1.92 tc-arm.c
*** tc-arm.c 2001/09/27 09:58:01 1.92
--- tc-arm.c 2001/10/08 17:23:03
***************
*** 56,61 ****
--- 56,62 ----
#define ARM_EXT_V5 0x00000080 /* Allow CLZ, etc. */
#define ARM_EXT_V5E 0x00000100 /* "El Segundo". */
#define ARM_EXT_XSCALE 0x00000200 /* Allow MIA etc. */
+ #define ARM_EXT_MAVERIK 0x00000400 /* Use Cirrus/DSP coprocessor. */
/* Architectures are the sum of the base and extensions. */
#define ARM_ARCH_V3M ARM_EXT_LONGMUL
*************** static CONST struct asm_psr psrs[] =
*** 579,584 ****
--- 580,596 ----
{"SPSR_cxsf", false, PSR_c | PSR_x | PSR_s | PSR_f},
};
+ enum cirrus_regtype
+ {
+ CIRRUS_REGTYPE_MVF = 1,
+ CIRRUS_REGTYPE_MVFX = 2,
+ CIRRUS_REGTYPE_MVD = 3,
+ CIRRUS_REGTYPE_MVDX = 4,
+ CIRRUS_REGTYPE_MVAX = 5,
+ CIRRUS_REGTYPE_DSPSC = 6,
+ CIRRUS_REGTYPE_ANY = 7
+ };
+
/* Functions called by parser. */
/* ARM instructions. */
static void do_arit PARAMS ((char *, unsigned long));
*************** static void do_fp_cmp PARAMS ((char *,
*** 642,647 ****
--- 654,684 ----
static void do_fp_from_reg PARAMS ((char *, unsigned long));
static void do_fp_to_reg PARAMS ((char *, unsigned long));
+ /* ARM_EXT_MAVERIK. */
+ static void do_c_binops PARAMS ((char *, unsigned long, int));
+ static void do_c_binops_1 PARAMS ((char *, unsigned long));
+ static void do_c_binops_2 PARAMS ((char *, unsigned long));
+ static void do_c_binops_3 PARAMS ((char *, unsigned long));
+ static void do_c_triple PARAMS ((char *, unsigned long, int));
+ static void do_c_triple_4 PARAMS ((char *, unsigned long));
+ static void do_c_triple_5 PARAMS ((char *, unsigned long));
+ static void do_c_quad PARAMS ((char *, unsigned long, int));
+ static void do_c_quad_6 PARAMS ((char *, unsigned long));
+ static void do_c_dspsc PARAMS ((char *, unsigned long, int));
+ static void do_c_dspsc_1 PARAMS ((char *, unsigned long));
+ static void do_c_dspsc_2 PARAMS ((char *, unsigned long));
+ static void do_c_shift PARAMS ((char *, unsigned long, int));
+ static void do_c_shift_1 PARAMS ((char *, unsigned long));
+ static void do_c_shift_2 PARAMS ((char *, unsigned long));
+ static void do_c_ldst PARAMS ((char *, unsigned long, int));
+ static void do_c_ldst_1 PARAMS ((char *, unsigned long));
+ static void do_c_ldst_2 PARAMS ((char *, unsigned long));
+ static void do_c_ldst_3 PARAMS ((char *, unsigned long));
+ static void do_c_ldst_4 PARAMS ((char *, unsigned long));
+ static int cirrus_reg_required_here PARAMS ((char **, int, enum cirrus_regtype));
+ static int cirrus_valid_reg PARAMS ((int, enum cirrus_regtype));
+ static int cirrus_parse_offset PARAMS ((char **, int *));
+
static void fix_new_arm PARAMS ((fragS *, int, short, expressionS *, int, int));
static int arm_reg_parse PARAMS ((char **));
static CONST struct asm_psr * arm_psr_parse PARAMS ((char **));
*************** static bfd_reloc_code_real_type arm_pars
*** 693,700 ****
/* LONGEST_INST is the longest basic instruction name without
conditions or flags. ARM7M has 4 of length 5. El Segundo
has one basic instruction name of length 7 (SMLALxy). */
! #define LONGEST_INST 7
struct asm_opcode
{
/* Basic string to match. */
--- 730,755 ----
/* LONGEST_INST is the longest basic instruction name without
conditions or flags. ARM7M has 4 of length 5. El Segundo
has one basic instruction name of length 7 (SMLALxy). */
! #define LONGEST_INST 10
!
! /* "INSN<cond> X,Y" where X:bit12, Y:bit16. */
! #define CIRRUS_MODE1 0x100c
!
! /* "INSN<cond> X,Y" where X:bit16, Y:bit12. */
! #define CIRRUS_MODE2 0x0c10
!
! /* "INSN<cond> X,Y" where X:0, Y:bit16. */
! #define CIRRUS_MODE3 0x1000
+ /* "INSN<cond> X,Y,Z" where X:16, Y:0, Z:12. */
+ #define CIRRUS_MODE4 0x0c0010
+
+ /* "INSN<cond> X,Y,Z" where X:12, Y:16, Z:0. */
+ #define CIRRUS_MODE5 0x00100c
+
+ /* "INSN<cond> W,X,Y,Z" where W:5, X:12, Y:16, Z:0. */
+ #define CIRRUS_MODE6 0x00100c05
+
struct asm_opcode
{
/* Basic string to match. */
*************** static CONST struct asm_opcode insns[] =
*** 885,890 ****
--- 940,1023 ----
{"mcrr", 0x0c400000, NULL, NULL, ARM_EXT_V5E, do_co_reg2c},
{"mrrc", 0x0c500000, NULL, NULL, ARM_EXT_V5E, do_co_reg2c},
+
+ /* Cirrus DSP instructions. */
+ {"cfldrs", 0x0c100400, NULL, NULL, ARM_EXT_MAVERIK, do_c_ldst_1},
+ {"cfldrd", 0x0c500400, NULL, NULL, ARM_EXT_MAVERIK, do_c_ldst_2},
+ {"cfldr32", 0x0c100500, NULL, NULL, ARM_EXT_MAVERIK, do_c_ldst_3},
+ {"cfldr64", 0x0c500500, NULL, NULL, ARM_EXT_MAVERIK, do_c_ldst_4},
+ {"cfstrs", 0x0c000400, NULL, NULL, ARM_EXT_MAVERIK, do_c_ldst_1},
+ {"cfstrd", 0x0c400400, NULL, NULL, ARM_EXT_MAVERIK, do_c_ldst_2},
+ {"cfstr32", 0x0c000500, NULL, NULL, ARM_EXT_MAVERIK, do_c_ldst_3},
+ {"cfstr64", 0x0c400500, NULL, NULL, ARM_EXT_MAVERIK, do_c_ldst_4},
+ {"cfmvsr", 0x0e000450, NULL, NULL, ARM_EXT_MAVERIK, do_c_binops_2},
+ {"cfmvrs", 0x0e100450, NULL, NULL, ARM_EXT_MAVERIK, do_c_binops_1},
+ {"cfmvdlr", 0x0e000410, NULL, NULL, ARM_EXT_MAVERIK, do_c_binops_2},
+ {"cfmvrdl", 0x0e100410, NULL, NULL, ARM_EXT_MAVERIK, do_c_binops_1},
+ {"cfmvdhr", 0x0e000430, NULL, NULL, ARM_EXT_MAVERIK, do_c_binops_2},
+ {"cfmvrdh", 0x0e100430, NULL, NULL, ARM_EXT_MAVERIK, do_c_binops_1},
+ {"cfmv64lr", 0x0e000510, NULL, NULL, ARM_EXT_MAVERIK, do_c_binops_2},
+ {"cfmvr64l", 0x0e100510, NULL, NULL, ARM_EXT_MAVERIK, do_c_binops_1},
+ {"cfmv64hr", 0x0e000530, NULL, NULL, ARM_EXT_MAVERIK, do_c_binops_2},
+ {"cfmvr64h", 0x0e100530, NULL, NULL, ARM_EXT_MAVERIK, do_c_binops_1},
+ {"cfmval32", 0x0e100610, NULL, NULL, ARM_EXT_MAVERIK, do_c_binops_3},
+ {"cfmv32al", 0x0e000610, NULL, NULL, ARM_EXT_MAVERIK, do_c_binops_3},
+ {"cfmvam32", 0x0e100630, NULL, NULL, ARM_EXT_MAVERIK, do_c_binops_3},
+ {"cfmv32am", 0x0e000630, NULL, NULL, ARM_EXT_MAVERIK, do_c_binops_3},
+ {"cfmvah32", 0x0e100650, NULL, NULL, ARM_EXT_MAVERIK, do_c_binops_3},
+ {"cfmv32ah", 0x0e000650, NULL, NULL, ARM_EXT_MAVERIK, do_c_binops_3},
+ {"cfmv32a", 0x0e000670, NULL, NULL, ARM_EXT_MAVERIK, do_c_binops_3},
+ {"cfmva32", 0x0e100670, NULL, NULL, ARM_EXT_MAVERIK, do_c_binops_3},
+ {"cfmv64a", 0x0e000690, NULL, NULL, ARM_EXT_MAVERIK, do_c_binops_3},
+ {"cfmva64", 0x0e100690, NULL, NULL, ARM_EXT_MAVERIK, do_c_binops_3},
+ {"cfmvsc32", 0x0e1006b0, NULL, NULL, ARM_EXT_MAVERIK, do_c_dspsc_1},
+ {"cfmv32sc", 0x0e0006b0, NULL, NULL, ARM_EXT_MAVERIK, do_c_dspsc_2},
+ {"cfcpys", 0x0e000400, NULL, NULL, ARM_EXT_MAVERIK, do_c_binops_1},
+ {"cfcpyd", 0x0e000420, NULL, NULL, ARM_EXT_MAVERIK, do_c_binops_1},
+ {"cfcvtsd", 0x0e000460, NULL, NULL, ARM_EXT_MAVERIK, do_c_binops_1},
+ {"cfcvtds", 0x0e000440, NULL, NULL, ARM_EXT_MAVERIK, do_c_binops_1},
+ {"cfcvt32s", 0x0e000480, NULL, NULL, ARM_EXT_MAVERIK, do_c_binops_1},
+ {"cfcvt32d", 0x0e0004a0, NULL, NULL, ARM_EXT_MAVERIK, do_c_binops_1},
+ {"cfcvt64s", 0x0e0004c0, NULL, NULL, ARM_EXT_MAVERIK, do_c_binops_1},
+ {"cfcvt64d", 0x0e0004e0, NULL, NULL, ARM_EXT_MAVERIK, do_c_binops_1},
+ {"cfcvts32", 0x0e100580, NULL, NULL, ARM_EXT_MAVERIK, do_c_binops_1},
+ {"cfcvtd32", 0x0e1005a0, NULL, NULL, ARM_EXT_MAVERIK, do_c_binops_1},
+ {"cftruncs32",0x0e1005c0, NULL, NULL, ARM_EXT_MAVERIK, do_c_binops_1},
+ {"cftruncd32",0x0e1005e0, NULL, NULL, ARM_EXT_MAVERIK, do_c_binops_1},
+ {"cfrshl32", 0x0e000550, NULL, NULL, ARM_EXT_MAVERIK, do_c_triple_4},
+ {"cfrshl64", 0x0e000570, NULL, NULL, ARM_EXT_MAVERIK, do_c_triple_4},
+ {"cfsh32", 0x0e000500, NULL, NULL, ARM_EXT_MAVERIK, do_c_shift_1},
+ {"cfsh64", 0x0e200500, NULL, NULL, ARM_EXT_MAVERIK, do_c_shift_2},
+ {"cfcmps", 0x0e100490, NULL, NULL, ARM_EXT_MAVERIK, do_c_triple_5},
+ {"cfcmpd", 0x0e1004b0, NULL, NULL, ARM_EXT_MAVERIK, do_c_triple_5},
+ {"cfcmp32", 0x0e100590, NULL, NULL, ARM_EXT_MAVERIK, do_c_triple_5},
+ {"cfcmp64", 0x0e1005b0, NULL, NULL, ARM_EXT_MAVERIK, do_c_triple_5},
+ {"cfabss", 0x0e300400, NULL, NULL, ARM_EXT_MAVERIK, do_c_binops_1},
+ {"cfabsd", 0x0e300420, NULL, NULL, ARM_EXT_MAVERIK, do_c_binops_1},
+ {"cfnegs", 0x0e300440, NULL, NULL, ARM_EXT_MAVERIK, do_c_binops_1},
+ {"cfnegd", 0x0e300460, NULL, NULL, ARM_EXT_MAVERIK, do_c_binops_1},
+ {"cfadds", 0x0e300480, NULL, NULL, ARM_EXT_MAVERIK, do_c_triple_5},
+ {"cfaddd", 0x0e3004a0, NULL, NULL, ARM_EXT_MAVERIK, do_c_triple_5},
+ {"cfsubs", 0x0e3004c0, NULL, NULL, ARM_EXT_MAVERIK, do_c_triple_5},
+ {"cfsubd", 0x0e3004e0, NULL, NULL, ARM_EXT_MAVERIK, do_c_triple_5},
+ {"cfmuls", 0x0e100400, NULL, NULL, ARM_EXT_MAVERIK, do_c_triple_5},
+ {"cfmuld", 0x0e100420, NULL, NULL, ARM_EXT_MAVERIK, do_c_triple_5},
+ {"cfabs32", 0x0e300500, NULL, NULL, ARM_EXT_MAVERIK, do_c_binops_1},
+ {"cfabs64", 0x0e300520, NULL, NULL, ARM_EXT_MAVERIK, do_c_binops_1},
+ {"cfneg32", 0x0e300540, NULL, NULL, ARM_EXT_MAVERIK, do_c_binops_1},
+ {"cfneg64", 0x0e300560, NULL, NULL, ARM_EXT_MAVERIK, do_c_binops_1},
+ {"cfadd32", 0x0e300580, NULL, NULL, ARM_EXT_MAVERIK, do_c_triple_5},
+ {"cfadd64", 0x0e3005a0, NULL, NULL, ARM_EXT_MAVERIK, do_c_triple_5},
+ {"cfsub32", 0x0e3005c0, NULL, NULL, ARM_EXT_MAVERIK, do_c_triple_5},
+ {"cfsub64", 0x0e3005e0, NULL, NULL, ARM_EXT_MAVERIK, do_c_triple_5},
+ {"cfmul32", 0x0e100500, NULL, NULL, ARM_EXT_MAVERIK, do_c_triple_5},
+ {"cfmul64", 0x0e100520, NULL, NULL, ARM_EXT_MAVERIK, do_c_triple_5},
+ {"cfmac32", 0x0e100540, NULL, NULL, ARM_EXT_MAVERIK, do_c_triple_5},
+ {"cfmsc32", 0x0e100560, NULL, NULL, ARM_EXT_MAVERIK, do_c_triple_5},
+ {"cfmadd32", 0x0e000600, NULL, NULL, ARM_EXT_MAVERIK, do_c_quad_6},
+ {"cfmsub32", 0x0e100600, NULL, NULL, ARM_EXT_MAVERIK, do_c_quad_6},
+ {"cfmadda32", 0x0e200600, NULL, NULL, ARM_EXT_MAVERIK, do_c_quad_6},
+ {"cfmsuba32", 0x0e300600, NULL, NULL, ARM_EXT_MAVERIK, do_c_quad_6},
};
/* Defines for various bits that we will want to toggle. */
*************** struct reg_entry
*** 1115,1120 ****
--- 1248,1263 ----
#define cp_register(reg) ((reg) >= 32 && (reg) <= 47)
#define fp_register(reg) ((reg) >= 16 && (reg) <= 23)
+ #define ARM_EXT_MAVERIKSC_REG 134
+
+ #define cirrus_register(reg) ((reg) >= 50 && (reg) <= 134)
+ #define cirrus_mvf_register(reg) ((reg) >= 50 && (reg) <= 65)
+ #define cirrus_mvd_register(reg) ((reg) >= 70 && (reg) <= 85)
+ #define cirrus_mvfx_register(reg) ((reg) >= 90 && (reg) <= 105)
+ #define cirrus_mvdx_register(reg) ((reg) >= 110 && (reg) <= 125)
+ #define cirrus_mvax_register(reg) ((reg) >= 130 && (reg) <= 133)
+ #define ARM_EXT_MAVERIKsc_register(reg) ((reg) == ARM_EXT_MAVERIKSC_REG)
+
#define REG_PC 15
#define REG_LR 14
#define REG_SP 13
*************** static CONST struct reg_entry reg_table[
*** 1150,1155 ****
--- 1293,1317 ----
{"s4",20}, {"s5",21}, {"s6",22}, {"s7",23},
{"d0",16}, {"d1",17}, {"d2",18}, {"d3",19},
{"d4",20}, {"d5",21}, {"d6",22}, {"d7",23},
+ /* Cirrus DSP coprocessor registers. */
+ {"mvf0", 50}, {"mvf1", 51}, {"mvf2", 52}, {"mvf3", 53},
+ {"mvf4", 54}, {"mvf5", 55}, {"mvf6", 56}, {"mvf7", 57},
+ {"mvf8", 58}, {"mvf9", 59}, {"mvf10", 60}, {"mvf11", 61},
+ {"mvf12", 62},{"mvf13", 63}, {"mvf14", 64}, {"mvf15", 65},
+ {"mvd0", 70}, {"mvd1", 71}, {"mvd2", 72}, {"mvd3", 73},
+ {"mvd4", 74}, {"mvd5", 75}, {"mvd6", 76}, {"mvd7", 77},
+ {"mvd8", 78}, {"mvd9", 79}, {"mvd10", 80}, {"mvd11", 81},
+ {"mvd12", 82},{"mvd13", 83}, {"mvd14", 84}, {"mvd15", 85},
+ {"mvfx0", 90},{"mvfx1", 91}, {"mvfx2", 92}, {"mvfx3", 93},
+ {"mvfx4", 94},{"mvfx5", 95}, {"mvfx6", 96}, {"mvfx7", 97},
+ {"mvfx8", 98},{"mvfx9", 99}, {"mvfx10", 100},{"mvfx11", 101},
+ {"mvfx12", 102},{"mvfx13", 103},{"mvfx14", 104},{"mvfx15", 105},
+ {"mvdx0", 110}, {"mvdx1", 111}, {"mvdx2", 112}, {"mvdx3", 113},
+ {"mvdx4", 114}, {"mvdx5", 115}, {"mvdx6", 116}, {"mvdx7", 117},
+ {"mvdx8", 118}, {"mvdx9", 119}, {"mvdx10", 120},{"mvdx11", 121},
+ {"mvdx12", 122},{"mvdx13", 123},{"mvdx14", 124},{"mvdx15", 125},
+ {"mvax0", 130}, {"mvax1", 131}, {"mvax2", 132}, {"mvax3", 133},
+ {"dspsc", ARM_EXT_MAVERIKSC_REG},
/* FIXME: At some point we need to add VFP register names. */
/* Array terminator. */
{NULL, 0}
*************** thumb_load_store (str, load_store, size)
*** 5982,5987 ****
--- 6144,6724 ----
end_of_line (str);
}
+ /* Given a register and a register type, return 1 if
+ the register is of the given type, else return 0. */
+
+ static int
+ cirrus_valid_reg (reg, regtype)
+ int reg;
+ enum cirrus_regtype regtype;
+ {
+ switch (regtype)
+ {
+ case CIRRUS_REGTYPE_ANY:
+ return 1;
+
+ case CIRRUS_REGTYPE_MVF:
+ return cirrus_mvf_register (reg);
+
+ case CIRRUS_REGTYPE_MVFX:
+ return cirrus_mvfx_register (reg);
+
+ case CIRRUS_REGTYPE_MVD:
+ return cirrus_mvd_register (reg);
+
+ case CIRRUS_REGTYPE_MVDX:
+ return cirrus_mvdx_register (reg);
+
+ case CIRRUS_REGTYPE_MVAX:
+ return cirrus_mvax_register (reg);
+
+ case CIRRUS_REGTYPE_DSPSC:
+ return ARM_EXT_MAVERIKsc_register (reg);
+ }
+
+ return 0;
+ }
+
+ /* A register must be given at this point.
+
+ If the register is a Cirrus register, convert it's reg# appropriately.
+
+ Shift is the place to put it in inst.instruction.
+
+ regtype is type register type expected, and is:
+ CIRRUS_REGTYPE_MVF
+ CIRRUS_REGTYPE_MVFX
+ CIRRUS_REGTYPE_MVD
+ CIRRUS_REGTYPE_MVDX
+ CIRRUS_REGTYPE_MVAX
+ CIRRUS_REGTYPE_DSPSC
+
+ Restores input start point on err.
+ Returns the reg#, or FAIL. */
+
+ static int
+ cirrus_reg_required_here (str, shift, regtype)
+ char ** str;
+ int shift;
+ enum cirrus_regtype regtype;
+ {
+ static char buff [135]; /* XXX */
+ int reg;
+ char * start = * str;
+
+ if ((reg = arm_reg_parse (str)) != FAIL
+ && (int_register (reg)
+ || cirrus_register (reg)))
+ {
+ int orig_reg = reg;
+
+ /* Calculate actual register # for opcode. */
+ if (cirrus_register (reg)
+ && !ARM_EXT_MAVERIKsc_register (reg)) /* Leave this one as is. */
+ {
+ if (reg >= 130)
+ reg -= 130;
+ else if (reg >= 110)
+ reg -= 110;
+ else if (reg >= 90)
+ reg -= 90;
+ else if (reg >= 70)
+ reg -= 70;
+ else if (reg >= 50)
+ reg -= 50;
+ }
+
+ if (!cirrus_valid_reg (orig_reg, regtype))
+ {
+ sprintf (buff, _("invalid register type at '%.100s'"), start);
+ inst.error = buff;
+ return FAIL;
+ }
+
+ if (shift >= 0)
+ inst.instruction |= reg << shift;
+
+ return orig_reg;
+ }
+
+ /* Restore the start point, we may have got a reg of the wrong class. */
+ *str = start;
+
+ /* In the few cases where we might be able to accept something else
+ this error can be overridden. */
+ sprintf (buff, _("Cirrus register expected, not '%.100s'"), start);
+ inst.error = buff;
+
+ return FAIL;
+ }
+
+ /* Cirrus Instructions. */
+
+ /* Wrapper functions. */
+
+ static void
+ do_c_binops_1 (str, flags)
+ char * str;
+ unsigned long flags;
+ {
+ do_c_binops (str, flags, CIRRUS_MODE1);
+ }
+
+ static void
+ do_c_binops_2 (str, flags)
+ char * str;
+ unsigned long flags;
+ {
+ do_c_binops (str, flags, CIRRUS_MODE2);
+ }
+
+ static void
+ do_c_binops_3 (str, flags)
+ char * str;
+ unsigned long flags;
+ {
+ do_c_binops (str, flags, CIRRUS_MODE3);
+ }
+
+ static void
+ do_c_triple_4 (str, flags)
+ char * str;
+ unsigned long flags;
+ {
+ do_c_triple (str, flags, CIRRUS_MODE4);
+ }
+
+ static void
+ do_c_triple_5 (str, flags)
+ char * str;
+ unsigned long flags;
+ {
+ do_c_triple (str, flags, CIRRUS_MODE5);
+ }
+
+ static void
+ do_c_quad_6 (str, flags)
+ char * str;
+ unsigned long flags;
+ {
+ do_c_quad (str, flags, CIRRUS_MODE6);
+ }
+
+ static void
+ do_c_dspsc_1 (str, flags)
+ char * str;
+ unsigned long flags;
+ {
+ do_c_dspsc (str, flags, CIRRUS_MODE1);
+ }
+
+ static void
+ do_c_dspsc_2 (str, flags)
+ char * str;
+ unsigned long flags;
+ {
+ do_c_dspsc (str, flags, CIRRUS_MODE2);
+ }
+
+ static void
+ do_c_shift_1 (str, flags)
+ char * str;
+ unsigned long flags;
+ {
+ do_c_shift (str, flags, CIRRUS_MODE1);
+ }
+
+ static void
+ do_c_shift_2 (str, flags)
+ char * str;
+ unsigned long flags;
+ {
+ do_c_shift (str, flags, CIRRUS_MODE2);
+ }
+
+ static void
+ do_c_ldst_1 (str, flags)
+ char * str;
+ unsigned long flags;
+ {
+ do_c_ldst (str, flags, CIRRUS_MODE1);
+ }
+
+ static void
+ do_c_ldst_2 (str, flags)
+ char * str;
+ unsigned long flags;
+ {
+ do_c_ldst (str, flags, CIRRUS_MODE2);
+ }
+
+ static void
+ do_c_ldst_3 (str, flags)
+ char * str;
+ unsigned long flags;
+ {
+ do_c_ldst (str, flags, CIRRUS_MODE3);
+ }
+
+ static void
+ do_c_ldst_4 (str, flags)
+ char * str;
+ unsigned long flags;
+ {
+ do_c_ldst (str, flags, CIRRUS_MODE4);
+ }
+
+ /* Isnsn like "foo X,Y". */
+
+ static void
+ do_c_binops (str, flags, mode)
+ char * str;
+ unsigned long flags;
+ int mode;
+ {
+ int shift1, shift2;
+
+ shift1 = mode & 0xff;
+ shift2 = (mode >> 8) & 0xff;
+
+ skip_whitespace (str);
+
+ if (cirrus_reg_required_here (&str, shift1, CIRRUS_REGTYPE_ANY) == FAIL
+ || skip_past_comma (&str) == FAIL
+ || cirrus_reg_required_here (&str, shift2, CIRRUS_REGTYPE_ANY) == FAIL)
+ {
+ if (!inst.error)
+ inst.error = BAD_ARGS;
+ }
+ else
+ end_of_line (str);
+
+ inst.instruction |= flags;
+ return;
+ }
+
+ /* Isnsn like "foo X,Y,Z". */
+
+ static void
+ do_c_triple (str, flags, mode)
+ char * str;
+ unsigned long flags;
+ int mode;
+ {
+ int shift1, shift2, shift3;
+
+ shift1 = mode & 0xff;
+ shift2 = (mode >> 8) & 0xff;
+ shift3 = (mode >> 16) & 0xff;
+
+ skip_whitespace (str);
+
+ if (cirrus_reg_required_here (&str, shift1, CIRRUS_REGTYPE_ANY) == FAIL
+ || skip_past_comma (&str) == FAIL
+ || cirrus_reg_required_here (&str, shift2, CIRRUS_REGTYPE_ANY) == FAIL
+ || skip_past_comma (&str) == FAIL
+ || cirrus_reg_required_here (&str, shift3, CIRRUS_REGTYPE_ANY) == FAIL)
+ {
+ if (!inst.error)
+ inst.error = BAD_ARGS;
+ }
+ else
+ end_of_line (str);
+
+ inst.instruction |= flags;
+ return;
+ }
+
+ /* Isnsn like "foo W,X,Y,Z".
+ where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
+
+ static void
+ do_c_quad (str, flags, mode)
+ char * str;
+ unsigned long flags;
+ int mode;
+ {
+ int shift1, shift2, shift3, shift4;
+ enum cirrus_regtype rt;
+
+ rt = (inst.instruction << 4 == 0xe2006000
+ || inst.instruction << 4 == 0xe3006000) ? CIRRUS_REGTYPE_MVAX
+ : CIRRUS_REGTYPE_MVFX;
+
+ shift1 = mode & 0xff;
+ shift2 = (mode >> 8) & 0xff;
+ shift3 = (mode >> 16) & 0xff;
+ shift4 = (mode >> 24) & 0xff;
+
+ skip_whitespace (str);
+
+ if (cirrus_reg_required_here (&str, shift1, CIRRUS_REGTYPE_MVAX) == FAIL
+ || skip_past_comma (&str) == FAIL
+ || cirrus_reg_required_here (&str, shift2, rt) == FAIL
+ || skip_past_comma (&str) == FAIL
+ || cirrus_reg_required_here (&str, shift3, CIRRUS_REGTYPE_MVFX) == FAIL
+ || skip_past_comma (&str) == FAIL
+ || cirrus_reg_required_here (&str, shift4, CIRRUS_REGTYPE_MVFX) == FAIL)
+ {
+ if (!inst.error)
+ inst.error = BAD_ARGS;
+ }
+ else
+ end_of_line (str);
+
+ inst.instruction |= flags;
+ return;
+ }
+
+ /* cfmvsc32<cond> DSPSC,MVFX[15:0].
+ cfmv32sc<cond> MVFX[15:0],DSPSC. */
+
+ static void
+ do_c_dspsc (str, flags, mode)
+ char * str;
+ unsigned long flags;
+ int mode;
+ {
+ int error;
+
+ skip_whitespace (str);
+
+ error = 0;
+
+ if (mode == CIRRUS_MODE1)
+ {
+ /* cfmvsc32. */
+ if (cirrus_reg_required_here (&str, -1, CIRRUS_REGTYPE_DSPSC) == FAIL
+ || skip_past_comma (&str) == FAIL
+ || cirrus_reg_required_here (&str, 16, CIRRUS_REGTYPE_MVFX) == FAIL)
+ error = 1;
+ }
+ else
+ {
+ /* cfmv32sc. */
+ if (cirrus_reg_required_here (&str, 0, CIRRUS_REGTYPE_MVFX) == FAIL
+ || skip_past_comma (&str) == FAIL
+ || cirrus_reg_required_here (&str, -1, CIRRUS_REGTYPE_DSPSC) == FAIL)
+ error = 1;
+ }
+
+ if (error)
+ {
+ if (!inst.error)
+ inst.error = BAD_ARGS;
+ }
+ else
+ {
+ inst.instruction |= flags;
+ end_of_line (str);
+ }
+
+ return;
+ }
+
+ /* Cirrus shift immediate instructions.
+ cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
+ cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
+
+ static void
+ do_c_shift (str, flags, mode)
+ char * str;
+ unsigned long flags;
+ int mode;
+ {
+ int error;
+ int imm, neg = 0;
+
+ skip_whitespace (str);
+
+ error = 0;
+
+ if (cirrus_reg_required_here (&str, 12,
+ (mode == CIRRUS_MODE1)
+ ? CIRRUS_REGTYPE_MVFX
+ : CIRRUS_REGTYPE_MVDX) == FAIL
+ || skip_past_comma (&str) == FAIL
+ || cirrus_reg_required_here (&str, 16,
+ (mode == CIRRUS_MODE1)
+ ? CIRRUS_REGTYPE_MVFX
+ : CIRRUS_REGTYPE_MVDX) == FAIL
+ || skip_past_comma (&str) == FAIL)
+ {
+ if (!inst.error)
+ inst.error = BAD_ARGS;
+ return;
+ }
+
+ /* Calculate the immediate operand.
+ The operand is a 7bit signed number. */
+ skip_whitespace (str);
+
+ if (*str == '#')
+ ++str;
+
+ if (!isdigit (*str) && *str != '-')
+ {
+ inst.error = _("expecting immediate, 7bit operand");
+ return;
+ }
+
+ if (*str == '-')
+ {
+ neg = 1;
+ ++str;
+ }
+
+ for (imm = 0; *str && isdigit (*str); ++str)
+ imm = imm * 10 + *str - '0';
+
+ if (imm > 64)
+ {
+ inst.error = _("immediate out of range");
+ return;
+ }
+
+ /* Make negative imm's into 7bit signed numbers. */
+ if (neg)
+ {
+ imm = -imm;
+ imm &= 0x0000007f;
+ }
+
+ /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
+ Bits 5-7 of the insn should have bits 4-6 of the immediate.
+ Bit 4 should be 0. */
+ imm = (imm & 0xf) | ((imm & 0x70) << 1);
+
+ inst.instruction |= imm;
+ inst.instruction |= flags;
+
+ end_of_line (str);
+
+ return;
+ }
+
+ static int
+ cirrus_parse_offset (str, negative)
+ char ** str;
+ int *negative;
+ {
+ char * p = *str;
+ int offset;
+
+ *negative = 0;
+
+ skip_whitespace (p);
+
+ if (*p == '#')
+ ++p;
+
+ if (*p == '-')
+ {
+ *negative = 1;
+ ++p;
+ }
+
+ if (!isdigit (*p))
+ {
+ inst.error = _("offset expected");
+ return 0;
+ }
+
+ for (offset = 0; *p && isdigit (*p); ++p)
+ offset = offset * 10 + *p - '0';
+
+ if (offset > 0xff)
+ {
+ inst.error = _("offset out of range");
+ return 0;
+ }
+
+ *str = p;
+
+ return *negative ? -offset : offset;
+ }
+
+ /* Cirrus load/store instructions.
+ <insn><cond> CRd,[Rn,<offset>]{!}.
+ <insn><cond> CRd,[Rn],<offset>. */
+
+ static void
+ do_c_ldst (str, flags, mode)
+ char * str;
+ unsigned long flags;
+ int mode;
+ {
+ int offset, negative;
+ enum cirrus_regtype rt;
+
+ rt = mode == CIRRUS_MODE1 ? CIRRUS_REGTYPE_MVF
+ : mode == CIRRUS_MODE2 ? CIRRUS_REGTYPE_MVD
+ : mode == CIRRUS_MODE3 ? CIRRUS_REGTYPE_MVFX
+ : mode == CIRRUS_MODE4 ? CIRRUS_REGTYPE_MVDX : CIRRUS_REGTYPE_MVF;
+
+ skip_whitespace (str);
+
+ if (cirrus_reg_required_here (& str, 12, rt) == FAIL
+ || skip_past_comma (& str) == FAIL
+ || *str++ != '['
+ || reg_required_here (& str, 16) == FAIL)
+ goto fail_ldst;
+
+ if (skip_past_comma (& str) == SUCCESS)
+ {
+ /* You are here: "<offset>]{!}". */
+ inst.instruction |= PRE_INDEX;
+
+ offset = cirrus_parse_offset (&str, &negative);
+
+ if (inst.error)
+ return;
+
+ if (*str++ != ']')
+ {
+ inst.error = _("missing ]");
+ return;
+ }
+
+ if (*str == '!')
+ {
+ inst.instruction |= WRITE_BACK;
+ ++str;
+ }
+ }
+ else
+ {
+ /* You are here: "], <offset>". */
+ if (*str++ != ']')
+ {
+ inst.error = _("missing ]");
+ return;
+ }
+
+ if (skip_past_comma (&str) == FAIL
+ || (offset = cirrus_parse_offset (&str, &negative), inst.error))
+ goto fail_ldst;
+
+ inst.instruction |= CP_T_WB; /* Post indexed, set bit W. */
+ }
+
+ if (negative)
+ offset = -offset;
+ else
+ inst.instruction |= CP_T_UD; /* Postive, so set bit U. */
+
+ inst.instruction |= offset >> 2;
+ inst.instruction |= flags;
+
+ end_of_line (str);
+ return;
+
+ fail_ldst:
+ if (!inst.error)
+ inst.error = BAD_ARGS;
+ return;
+ }
+
static void
do_t_nop (str)
char * str;
*************** _("Warning: Use of the 'nv' conditional
*** 7907,7912 ****
--- 8644,8650 ----
-m[arm]7[xx][t][[d]m] Arm 7 processors
-m[arm]8[10] Arm 8 processors
-m[arm]9[20][tdmi] Arm 9 processors
+ -marm9e Allow Cirrus/DSP instructions
-mstrongarm[110[0]] StrongARM processors
-mxscale XScale processors
-m[arm]v[2345[t[e]]] Arm architectures
*************** md_parse_option (c, arg)
*** 8189,8194 ****
--- 8927,8935 ----
else if (streq (str, "9tdmi"))
cpu_variant = (cpu_variant & ~ARM_ANY)
| ARM_9 | ARM_ARCH_V4T;
+ else if (streq (str, "9e"))
+ cpu_variant = (cpu_variant & ~ARM_ANY)
+ | ARM_9 | ARM_ARCH_V4T | ARM_EXT_MAVERIK;
else
goto bad;
break;
*************** md_show_usage (fp)
*** 8304,8309 ****
--- 9045,9051 ----
ARM Specific Assembler Options:\n\
-m[arm][<processor name>] select processor variant\n\
-m[arm]v[2|2a|3|3m|4|4t|5[t][e]] select architecture variant\n\
+ -marm9e allow Cirrus/DSP instructions\n\
-mthumb only allow Thumb instructions\n\
-mthumb-interwork mark the assembled code as supporting interworking\n\
-mall allow any instruction\n\
Index: gas/doc/c-arm.texi
===================================================================
RCS file: /cvs/uberbaum/gas/doc/c-arm.texi,v
retrieving revision 1.11
diff -c -p -r1.11 c-arm.texi
*** c-arm.texi 2001/03/08 23:24:26 1.11
--- c-arm.texi 2001/10/08 17:23:03
***************
*** 34,42 ****
--- 34,46 ----
@cindex @code{-marm} command line option, ARM
@item -marm@code{[2|250|3|6|60|600|610|620|7|7m|7d|7dm|7di|7dmi|70|700|700i|710|710c|7100|7500|7500fe|7tdmi|8|810|9|9tdmi|920|strongarm|strongarm110|strongarm1100]}
@itemx -mxscale
+ @itemx -marm9e
This option specifies the target processor. The assembler will issue an
error message if an attempt is made to assemble an instruction which
will not execute on the target processor.
+
+ The option @code{-marm9e} specifies that the target processor is the
+ Cirrus ARM processor with the Maverick DSP co-processor.
@cindex @code{-marmv} command line option, ARM
@item -marmv@code{[2|2a|3|3m|4|4t|5|5t|5te]}
Index: gas/testsuite/gas/arm/arm.exp
===================================================================
RCS file: /cvs/uberbaum/gas/testsuite/gas/arm/arm.exp,v
retrieving revision 1.6
diff -c -p -r1.6 arm.exp
*** arm.exp 2001/06/21 19:46:54 1.6
--- arm.exp 2001/10/08 17:23:03
*************** if [istarget arm-*-pe] {
*** 40,42 ****
--- 40,45 ----
# Since big-endian numbers have the normal format, this doesn't exist.
#run_dump_test "be-fpconst"
}
+ if [istarget arm9e-*] {
+ run_dump_test "maverick"
+ }
Index: ld/configure.tgt
===================================================================
RCS file: /cvs/uberbaum/ld/configure.tgt,v
retrieving revision 1.63
diff -c -p -r1.63 configure.tgt
*** configure.tgt 2001/09/14 11:46:37 1.63
--- configure.tgt 2001/10/08 17:23:03
*************** arm-*-netbsd*) targ_emul=armnbsd ;;
*** 200,205 ****
--- 200,206 ----
arm-*-openbsd*) targ_emul=armnbsd ;;
arm-*-rtems*) targ_emul=armelf ;;
arm-*-elf) targ_emul=armelf ;;
+ arm9e-*-elf) targ_emul=armelf ;;
arm-*-oabi) targ_emul=armelf_oabi ;;
arm*-*-linux-gnu*) targ_emul=armelf_linux; targ_extra_emuls=armelf ;;
arm*-*-uclinux*) targ_emul=armelf_linux; targ_extra_emuls=armelf ;;
Index: opcodes/arm-dis.c
===================================================================
RCS file: /cvs/uberbaum/opcodes/arm-dis.c,v
retrieving revision 1.24
diff -c -p -r1.24 arm-dis.c
*** arm-dis.c 2001/09/19 17:40:28 1.24
--- arm-dis.c 2001/10/08 17:23:04
*************** print_insn_arm (pc, info, given)
*** 445,450 ****
--- 445,469 ----
}
break;
+ case 'I':
+ /* Print a Cirrus/DSP shift immediate. */
+ /* Immediates are 7bit signed ints with bits 0..3 in
+ bits 0..3 of opcode and bits 4..6 in bits 5..7
+ of opcode. */
+ {
+ int imm;
+
+ imm = (given & 0xf) | ((given & 0xe0) >> 1);
+
+ /* Is ``imm'' a negative number? */
+ if (imm & 0x40)
+ imm |= (-1 << 7);
+
+ func (stream, "%d", imm);
+ }
+
+ break;
+
case 'C':
func (stream, "_");
if (given & 0x80000)
Index: opcodes/arm-opc.h
===================================================================
RCS file: /cvs/uberbaum/opcodes/arm-opc.h,v
retrieving revision 1.7
diff -c -p -r1.7 arm-opc.h
*** arm-opc.h 2001/03/13 22:58:34 1.7
--- arm-opc.h 2001/10/08 17:23:04
*************** Thumb specific format options:
*** 66,71 ****
--- 66,72 ----
%N print Thumb register mask (with LR)
%O print Thumb register mask (with PC)
%T print Thumb condition code (always bits 8-11)
+ %I print cirrus signed shift immediate: bits 0..3|4..6
%<bitfield>B print Thumb branch destination (signed displacement)
%<bitfield>W print (bitfield * 4) as a decimal
%<bitfield>H print (bitfield * 2) as a decimal
*************** static struct arm_opcode arm_opcodes[] =
*** 212,217 ****
--- 213,304 ----
{0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
{0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
{0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
+
+ /* Cirrus coprocessor instructions. */
+ {0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
+ {0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
+ {0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
+ {0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
+ {0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
+ {0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
+ {0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
+ {0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
+ {0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
+ {0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
+ {0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
+ {0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
+ {0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
+ {0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
+ {0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
+ {0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
+ {0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
+ {0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
+ {0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
+ {0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
+ {0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
+ {0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
+ {0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
+ {0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
+ {0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
+ {0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
+ {0x0e100610, 0x0ff0fff0, "cfmval32%c\tmvax%0-3d, mvfx%16-19d"},
+ {0x0e000610, 0x0ff0fff0, "cfmv32al%c\tmvfx%0-3d, mvax%16-19d"},
+ {0x0e100630, 0x0ff0fff0, "cfmvam32%c\tmvax%0-3d, mvfx%16-19d"},
+ {0x0e000630, 0x0ff0fff0, "cfmv32am%c\tmvfx%0-3d, mvax%16-19d"},
+ {0x0e100650, 0x0ff0fff0, "cfmvah32%c\tmvax%0-3d, mvfx%16-19d"},
+ {0x0e000650, 0x0ff0fff0, "cfmv32ah%c\tmvfx%0-3d, mvax%16-19d"},
+ {0x0e000670, 0x0ff0fff0, "cfmv32a%c\tmvfx%0-3d, mvax%16-19d"},
+ {0x0e100670, 0x0ff0fff0, "cfmva32%c\tmvax%0-3d, mvfx%16-19d"},
+ {0x0e000690, 0x0ff0fff0, "cfmv64a%c\tmvdx%0-3d, mvax%16-19d"},
+ {0x0e100690, 0x0ff0fff0, "cfmva64%c\tmvax%0-3d, mvdx%16-19d"},
+ {0x0e1006b0, 0x0ff0fff0, "cfmvsc32%c\tdspsc, mvfx%16-19d"},
+ {0x0e0006b0, 0x0ff0fff0, "cfmv32sc%c\tmvfx%0-3d, dspsc"},
+ {0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
+ {0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
+ {0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
+ {0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
+ {0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
+ {0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
+ {0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
+ {0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
+ {0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
+ {0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
+ {0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
+ {0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
+ {0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
+ {0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
+ {0x0e000500, 0x0ff00f00, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
+ {0x0e200500, 0x0ff00f00, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
+ {0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
+ {0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
+ {0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
+ {0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
+ {0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
+ {0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
+ {0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
+ {0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
+ {0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
+ {0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
+ {0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
+ {0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
+ {0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
+ {0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
+ {0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
+ {0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
+ {0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
+ {0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
+ {0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
+ {0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
+ {0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
+ {0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
+ {0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
+ {0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
+ {0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
+ {0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
+ {0x0e000600, 0x0ff00f00, "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
+ {0x0e100600, 0x0ff00f00, "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
+ {0x0e200600, 0x0ff00f00, "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
+ {0x0e300600, 0x0ff00f00, "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
/* Generic coprocessor instructions */
{0x0e000000, 0x0f000010, "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
*** /dev/null Sat Mar 24 00:37:44 2001
--- maverick.c Mon Oct 8 13:10:18 2001
***************
*** 0 ****
--- 1,499 ----
+ /* Copyright (C) 2000 Free Software Foundation
+ * Contributed by Alexandre Oliva <aoliva@cygnus.com>
+ *
+ * This file is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+ /* Generator of tests for Maverick.
+ *
+ * See the following file for usage and documentation. */
+ #include "../all/test-gen.c"
+
+ /* These are the ARM registers. Some of them have canonical names
+ * other than r##, so we'll use both in the asm input, but only the
+ * canonical names in the expected disassembler output. */
+ char *arm_regs[] = {
+ /* Canonical names. */
+ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
+ "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc",
+ /* Alternate names, i.e., those that can be used in the assembler,
+ * but that will never be emitted by the disassembler. */
+ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
+ "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
+ };
+
+ /* The various types of registers: ARM's registers, Maverick's
+ * f/d/fx/dx registers, Maverick's accumulators and Maverick's status
+ * register. */
+ #define armreg(shift) \
+ reg_r (arm_regs, shift, 0xf, mk_get_bits (5u))
+ #define mvreg(prefix, shift) \
+ reg_p ("mv" prefix, shift, mk_get_bits (4u))
+ #define acreg(shift) \
+ reg_p ("mvax", shift, mk_get_bits (2u))
+ #define dspsc \
+ literal ("dspsc"), tick_random
+
+ /* This outputs the condition flag that may follow each ARM insn.
+ * Since the condition 15 is invalid, we use it to check that the
+ * assembler recognizes the absence of a condition as `al'. However,
+ * the disassembler won't ever output `al', so, if we emit it in the
+ * assembler, expect the condition to be omitted in the disassembler
+ * output. */
+ int
+ arm_cond (func_arg *arg, insn_data *data)
+ #define arm_cond { arm_cond }
+ {
+ static const char conds[16][3] = {
+ "eq", "ne", "cs", "cc",
+ "mi", "pl", "vs", "vc",
+ "hi", "ls", "ge", "lt",
+ "gt", "le", "al", ""
+ };
+ unsigned val = get_bits (4u);
+
+ data->as_in = data->dis_out = strdup (conds[val]);
+ if (val == 14)
+ data->dis_out = strdup ("");
+ data->bits = (val == 15 ? 14 : val) << 28;
+ return 0;
+ }
+
+ /* The sign of an offset is actually used to determined whether the
+ * absolute value of the offset should be added or subtracted, so we
+ * must adjust negative values so that they do not overflow: -256 is
+ * not valid, but -0 is distinct from +0. */
+ int
+ off8s (func_arg *arg, insn_data *data)
+ #define off8s { off8s }
+ {
+ int val = get_bits (9s);
+ char value[6], *strt = value;
+ *strt++ = '#';
+ if (val < 0)
+ {
+ *strt++ = '-';
+ ++val;
+ val = -val;
+ data->bits = val;
+ }
+ else
+ data->bits = val | (1 << 23);
+ sprintf (strt, "%i", val);
+ data->as_in = data->dis_out = strdup (value);
+ return 0;
+ }
+
+ /* This function generates a 7-bit signed constant, emitted as
+ * follows: the 4 least-significant bits are stored in the 4
+ * least-significant bits of the word; the 3 most-significant bits are
+ * stored in bits 7:5, i.e., bit 4 is skipped. */
+ int
+ imm7 (func_arg *arg, insn_data *data)
+ #define imm7 { imm7 }
+ {
+ int val = get_bits (7s);
+ char value[6];
+
+ data->bits = (val & 0x0f) | (2 * (val & 0x70));
+ sprintf (value, "#%i", val);
+ data->as_in = data->dis_out = strdup (value);
+ return 0;
+ }
+
+ /* Convenience wrapper to define_insn, that prefixes every insn with
+ * `cf' (so, if you specify command-line arguments, remember that `cf'
+ * must *not* be part of the string), and post-fixes a condition code.
+ * insname and insnvar specify the main insn name and a variant;
+ * they're just concatenated, and insnvar is often empty. word is the
+ * bit pattern that defines the insn, properly shifted, and funcs is a
+ * sequence of funcs that define the operands and the syntax of the
+ * insn. */
+ #define mv_insn(insname, insnvar, word, funcs...) \
+ define_insn(insname ## insnvar, \
+ literal ("cf"), \
+ insn_bits (insname, word), \
+ arm_cond, \
+ tab, \
+ ## funcs)
+
+ /* Define a single LDC/STC variant. op is the main insn opcode; ld
+ * stands for load (it should be 0 on stores), dword selects 64-bit
+ * operations, pre should be enabled for pre-increment, and wb, for
+ * write-back. sep1, sep2 and sep3 are syntactical elements ([]!)
+ * that the assembler will use to enable pre and wb. It would
+ * probably have been cleaner to couple the syntactical elements with
+ * the pre/wb bits directly, but it would have required the definition
+ * of more functions. */
+ #define LDST(insname, insnvar, op, ld, dword, regname, pre, wb, sep1, sep2, sep3) \
+ mv_insn (insname, insnvar, \
+ (12<<24)|(op<<8)|(ld<<20)|(pre<<24)|(dword<<22)|(wb<<21), \
+ mvreg (regname, 12), comma, \
+ lsqbkt, armreg (16), sep1, comma, off8s, sep2, sep3, \
+ tick_random)
+
+ /* Define all variants of an LDR or STR instruction, namely,
+ * pre-indexed without write-back, pre-indexed with write-back and
+ * post-indexed. */
+ #define LDSTall(insname, op, ld, dword, regname) \
+ LDST (insname, _p, op, ld, dword, regname, 1, 0, nothing, rsqbkt, nothing); \
+ LDST (insname, _pw, op, ld, dword, regname, 1, 1, nothing, rsqbkt, literal("!")); \
+ LDST (insname, ,op, ld, dword, regname, 0, 0, rsqbkt, nothing, nothing)
+
+ /* Produce the insn identifiers of all LDST variants of a given insn.
+ * To be used in the initialization of an insn group array. */
+ #define insns_LDSTall(insname) \
+ insn (insname ## _p), insn (insname ## _pw), insn (insname)
+
+ /* Define a CDP variant that uses two registers, at offsets 12 and 16.
+ * The two opcodes and the co-processor number identify the CDP
+ * insn. */
+ #define CDP2(insname, var, cpnum, opcode1, opcode2, reg1name, reg2name) \
+ mv_insn (insname##var, , \
+ (14<<24)|((opcode1)<<20)|((cpnum)<<8)|((opcode2)<<5), \
+ mvreg (reg1name, 12), comma, mvreg (reg2name, 16))
+
+ /* Define a 32-bit integer CDP instruction with two operands. */
+ #define CDP2fx(insname, opcode1, opcode2) \
+ CDP2 (insname, 32, 5, opcode1, opcode2, "fx", "fx")
+
+ /* Define a 64-bit integer CDP instruction with two operands. */
+ #define CDP2dx(insname, opcode1, opcode2) \
+ CDP2 (insname, 64, 5, opcode1, opcode2, "dx", "dx")
+
+ /* Define a float CDP instruction with two operands. */
+ #define CDP2f(insname, opcode1, opcode2) \
+ CDP2 (insname, s, 4, opcode1, opcode2, "f", "f")
+
+ /* Define a double CDP instruction with two operands. */
+ #define CDP2d(insname, opcode1, opcode2) \
+ CDP2 (insname, d, 4, opcode1, opcode2, "d", "d")
+
+ /* Define a CDP instruction with two register operands and one 7-bit
+ * signed immediate generated with imm7. */
+ #define CDP2_imm7(insname, cpnum, opcode1, reg1name, reg2name) \
+ mv_insn (insname, , (14<<24)|((opcode1)<<20)|((cpnum)<<8), \
+ mvreg (reg1name, 12), comma, mvreg (reg2name, 16), comma, imm7, \
+ tick_random)
+
+ /* Produce the insn identifiers of CDP floating-point or integer insn
+ * pairs (i.e., it appends the suffixes for 32-bit and 64-bit
+ * insns. */
+ #define CDPfp_insns(insname) \
+ insn (insname ## s), insn (insname ## d)
+ #define CDPx_insns(insname) \
+ insn (insname ## 32), insn (insname ## 64)
+
+ /* Define a CDP instruction with 3 operands, at offsets 12, 16, 0. */
+ #define CDP3(insname, var, cpnum, opcode1, opcode2, reg1name, reg2name, reg3name) \
+ mv_insn (insname##var, , \
+ (14<<24)|((opcode1)<<20)|((cpnum)<<8)|((opcode2)<<5), \
+ mvreg (reg1name, 12), comma, mvreg (reg2name, 16), comma, \
+ mvreg (reg3name, 0), tick_random)
+
+ /* Define a 32-bit integer CDP instruction with three operands. */
+ #define CDP3fx(insname, opcode1, opcode2) \
+ CDP3 (insname, 32, 5, opcode1, opcode2, "fx", "fx", "fx")
+
+ /* Define a 64-bit integer CDP instruction with three operands. */
+ #define CDP3dx(insname, opcode1, opcode2) \
+ CDP3 (insname, 64, 5, opcode1, opcode2, "dx", "dx", "dx")
+
+ /* Define a float CDP instruction with three operands. */
+ #define CDP3f(insname, opcode1, opcode2) \
+ CDP3 (insname, s, 4, opcode1, opcode2, "f", "f", "f")
+
+ /* Define a double CDP instruction with three operands. */
+ #define CDP3d(insname, opcode1, opcode2) \
+ CDP3 (insname, d, 4, opcode1, opcode2, "d", "d", "d")
+
+ /* Define a CDP instruction with four operands, at offsets 5, 12, 16
+ * and 0. Used only for ACC instructions. */
+ #define CDP4(insname, opcode1, reg2spec, reg3name, reg4name) \
+ mv_insn (insname, , (14<<24)|((opcode1)<<20)|(6<<8), \
+ acreg (5), comma, reg2spec, comma, \
+ mvreg (reg3name, 16), comma, mvreg (reg4name, 0))
+
+ /* Define a CDP4 instruction with one accumulator operands. */
+ #define CDP41A(insname, opcode1) \
+ CDP4 (insname, opcode1, mvreg ("fx", 12), "fx", "fx")
+
+ /* Define a CDP4 instruction with two accumulator operands. */
+ #define CDP42A(insname, opcode1) \
+ CDP4 (insname, opcode1, acreg (12), "fx", "fx")
+
+ /* Define a MCR or MRC instruction with two register operands. */
+ #define MCRC2(insname, cpnum, opcode1, dir, opcode2, reg1spec, reg2spec) \
+ mv_insn (insname, , \
+ ((14<<24)|((opcode1)<<21)|((dir)<<20)| \
+ ((cpnum)<<8)|((opcode2)<<5)|(1<<4)), \
+ reg1spec, comma, reg2spec)
+
+ /* Define a move from a DSP register to an ARM register. */
+ #define MVDSPARM(insname, cpnum, opcode2, regDSPname) \
+ MCRC2 (mv ## insname, cpnum, 0, 0, opcode2, \
+ mvreg (regDSPname, 16), armreg(12))
+
+ /* Define a move from an ARM register to a DSP register. */
+ #define MVARMDSP(insname, cpnum, opcode2, regDSPname) \
+ MCRC2 (mv ## insname, cpnum, 0, 1, opcode2, \
+ armreg (12), mvreg (regDSPname, 16))
+
+ /* Define a move from a DSP register to a DSP accumulator. */
+ #define MVDSPACC(insname, opcode2, regDSPname) \
+ MCRC2 (mv ## insname, 6, 0, 1, opcode2, acreg (0), mvreg (regDSPname, 16))
+
+ /* Define a move from a DSP accumulator to a DSP register. */
+ #define MVACCDSP(insname, opcode2, regDSPname) \
+ MCRC2 (mv ## insname, 6, 0, 0, opcode2, mvreg (regDSPname, 0), acreg (16))
+
+ /* Define move insns between a float DSP register and an ARM
+ * register. */
+ #define MVf(nameAD, nameDA, opcode2) \
+ MVDSPARM (nameAD, 4, opcode2, "f"); \
+ MVARMDSP (nameDA, 4, opcode2, "f")
+
+ /* Define move insns between a double DSP register and an ARM
+ * register. */
+ #define MVd(nameAD, nameDA, opcode2) \
+ MVDSPARM (nameAD, 4, opcode2, "d"); \
+ MVARMDSP (nameDA, 4, opcode2, "d")
+
+ /* Define move insns between a 32-bit integer DSP register and an ARM
+ * register. */
+ #define MVfx(nameAD, nameDA, opcode2) \
+ MVDSPARM (nameAD, 5, opcode2, "fx"); \
+ MVARMDSP (nameDA, 5, opcode2, "fx")
+
+ /* Define move insns between a 64-bit integer DSP register and an ARM
+ * register. */
+ #define MVdx(nameAD, nameDA, opcode2) \
+ MVDSPARM (nameAD, 5, opcode2, "dx"); \
+ MVARMDSP (nameDA, 5, opcode2, "dx")
+
+ /* Define move insns between a 32-bit DSP register and a DSP
+ * accumulator. */
+ #define MVfxa(nameFA, nameAF, opcode2) \
+ MVDSPACC (nameFA, opcode2, "fx"); \
+ MVACCDSP (nameAF, opcode2, "fx")
+
+ /* Define move insns between a 64-bit DSP register and a DSP
+ * accumulator. */
+ #define MVdxa(nameDA, nameAD, opcode2) \
+ MVDSPACC (nameDA, opcode2, "dx"); \
+ MVACCDSP (nameAD, opcode2, "dx")
+
+ /* Produce the insn identifiers for a pair of mv insns. */
+ #define insns_MV(name1, name2) \
+ insn (mv ## name1), insn (mv ## name2)
+
+ /* Define a MCR or MRC instruction with three register operands. */
+ #define MCRC3(insname, cpnum, opcode1, dir, opcode2, reg1spec, reg2spec, reg3spec) \
+ mv_insn (insname, , \
+ ((14<<24)|((opcode1)<<21)|((dir)<<20)| \
+ ((cpnum)<<8)|((opcode2)<<5)|(1<<4)), \
+ reg1spec, comma, reg2spec, comma, reg3spec, \
+ tick_random)
+
+ /* Define all load_store insns. */
+ LDSTall (ldrs, 4, 1, 0, "f");
+ LDSTall (ldrd, 4, 1, 1, "d");
+ LDSTall (ldr32, 5, 1, 0, "fx");
+ LDSTall (ldr64, 5, 1, 1, "dx");
+ LDSTall (strs, 4, 0, 0, "f");
+ LDSTall (strd, 4, 0, 1, "d");
+ LDSTall (str32, 5, 0, 0, "fx");
+ LDSTall (str64, 5, 0, 1, "dx");
+
+ /* Create the load_store insn group. */
+ func *load_store_insns[] = {
+ insns_LDSTall (ldrs), insns_LDSTall (ldrd),
+ insns_LDSTall (ldr32), insns_LDSTall (ldr64),
+ insns_LDSTall (strs), insns_LDSTall (strd),
+ insns_LDSTall (str32), insns_LDSTall (str64),
+ 0
+ };
+
+ /* Define all move insns. */
+ MVf (sr, rs, 2);
+ MVd (dlr, rdl, 0);
+ MVd (dhr, rdh, 1);
+ MVdx (64lr, r64l, 0);
+ MVdx (64hr, r64h, 1);
+ MVfxa (al32, 32al, 0);
+ MVfxa (am32, 32am, 1);
+ MVfxa (ah32, 32ah, 2);
+ MVfxa (a32, 32a, 3);
+ MVdxa (a64, 64a, 4);
+ MCRC2 (mvsc32, 6, 0, 1, 5, dspsc, mvreg ("fx", 16));
+ MCRC2 (mv32sc, 6, 0, 0, 5, mvreg ("fx", 0), dspsc);
+ CDP2 (cpys, , 4, 0, 0, "f", "f");
+ CDP2 (cpyd, , 4, 0, 1, "d", "d");
+
+ /* Create the move insns group. */
+ func *move_insns[] = {
+ insns_MV (sr, rs), insns_MV (dlr, rdl), insns_MV (dhr, rdh),
+ insns_MV (64lr, r64l), insns_MV (64hr, r64h),
+ insns_MV (al32, 32al), insns_MV (am32, 32am), insns_MV (ah32, 32ah),
+ insns_MV (a32, 32a), insns_MV (a64, 64a),
+ insn (mvsc32), insn (mv32sc), insn (cpys), insn (cpyd),
+ 0
+ };
+
+ /* Define all conversion insns. */
+ CDP2 (cvtsd, , 4, 0, 3, "d", "f");
+ CDP2 (cvtds, , 4, 0, 2, "f", "d");
+ CDP2 (cvt32s, , 4, 0, 4, "f", "fx");
+ CDP2 (cvt32d, , 4, 0, 5, "d", "fx");
+ CDP2 (cvt64s, , 4, 0, 6, "f", "dx");
+ CDP2 (cvt64d, , 4, 0, 7, "d", "dx");
+ CDP2 (cvts32, , 5, 1, 4, "fx", "f");
+ CDP2 (cvtd32, , 5, 1, 5, "fx", "d");
+ CDP2 (truncs32, , 5, 1, 6, "fx", "f");
+ CDP2 (truncd32, , 5, 1, 7, "fx", "d");
+
+ /* Create the conv insns group. */
+ func *conv_insns[] = {
+ insn (cvtsd), insn (cvtds), insn (cvt32s), insn (cvt32d),
+ insn (cvt64s), insn (cvt64d), insn (cvts32), insn (cvtd32),
+ insn (truncs32), insn (truncd32),
+ 0
+ };
+
+ /* Define all shift insns. */
+ MCRC3 (rshl32, 5, 0, 0, 2, mvreg ("fx", 16), mvreg ("fx", 0), armreg(12));
+ MCRC3 (rshl64, 5, 0, 0, 3, mvreg ("dx", 16), mvreg ("dx", 0), armreg(12));
+ CDP2_imm7 (sh32, 5, 0, "fx", "fx");
+ CDP2_imm7 (sh64, 5, 2, "dx", "dx");
+
+ /* Create the shift insns group. */
+ func *shift_insns[] = {
+ insn (rshl32), insn (rshl64),
+ insn (sh32), insn (sh64),
+ 0
+ };
+
+ /* Define all comparison insns. */
+ MCRC3 (cmps, 4, 0, 1, 4, armreg (12), mvreg ("f", 16), mvreg ("f", 0));
+ MCRC3 (cmpd, 4, 0, 1, 5, armreg (12), mvreg ("d", 16), mvreg ("d", 0));
+ MCRC3 (cmp32, 5, 0, 1, 4, armreg (12), mvreg ("fx", 16), mvreg ("fx", 0));
+ MCRC3 (cmp64, 5, 0, 1, 5, armreg (12), mvreg ("dx", 16), mvreg ("dx", 0));
+
+ /* Create the comp insns group. */
+ func *comp_insns[] = {
+ insn (cmps), insn (cmpd),
+ insn (cmp32), insn (cmp64),
+ 0
+ };
+
+ /* Define all floating-point arithmetic insns. */
+ CDP2f (abs, 3, 0);
+ CDP2d (abs, 3, 1);
+ CDP2f (neg, 3, 2);
+ CDP2d (neg, 3, 3);
+ CDP3f (add, 3, 4);
+ CDP3d (add, 3, 5);
+ CDP3f (sub, 3, 6);
+ CDP3d (sub, 3, 7);
+ CDP3f (mul, 1, 0);
+ CDP3d (mul, 1, 1);
+
+ /* Create the fp-arith insns group. */
+ func *fp_arith_insns[] = {
+ CDPfp_insns (abs), CDPfp_insns (neg),
+ CDPfp_insns (add), CDPfp_insns (sub), CDPfp_insns (mul),
+ 0
+ };
+
+ /* Define all integer arithmetic insns. */
+ CDP2fx (abs, 3, 0);
+ CDP2dx (abs, 3, 1);
+ CDP2fx (neg, 3, 2);
+ CDP2dx (neg, 3, 3);
+ CDP3fx (add, 3, 4);
+ CDP3dx (add, 3, 5);
+ CDP3fx (sub, 3, 6);
+ CDP3dx (sub, 3, 7);
+ CDP3fx (mul, 1, 0);
+ CDP3dx (mul, 1, 1);
+ CDP3fx (mac, 1, 2);
+ CDP3fx (msc, 1, 3);
+
+ /* Create the int-arith insns group. */
+ func *int_arith_insns[] = {
+ CDPx_insns (abs), CDPx_insns (neg),
+ CDPx_insns (add), CDPx_insns (sub), CDPx_insns (mul),
+ insn (mac32), insn (msc32),
+ 0
+ };
+
+ /* Define all accumulator arithmetic insns. */
+ CDP41A (madd32, 0);
+ CDP41A (msub32, 1);
+ CDP42A (madda32, 2);
+ CDP42A (msuba32, 3);
+
+ /* Create the acc-arith insns group. */
+ func *acc_arith_insns[] = {
+ insn (madd32), insn (msub32),
+ insn (madda32), insn (msuba32),
+ 0
+ };
+
+ /* Create the set of all groups. */
+ group_t
+ groups[] = {
+ { "load_store", load_store_insns },
+ { "move", move_insns },
+ { "conv", conv_insns },
+ { "shift", shift_insns },
+ { "comp", comp_insns },
+ { "fp_arith", fp_arith_insns },
+ { "int_arith", int_arith_insns },
+ { "acc_arith", acc_arith_insns },
+ { 0 }
+ };
+
+ int
+ main(int argc, char *argv[])
+ {
+ FILE *as_in = stdout, *dis_out = stderr;
+
+ /* Check whether we're filtering insns. */
+ if (argc > 1)
+ skip_list = argv + 1;
+
+ /* Output assembler header. */
+ fputs ("\t.text\n"
+ "\t.align\n",
+ as_in);
+ /* Output comments for the testsuite-driver and the initial
+ * disassembler output. */
+ fputs ("#objdump: -dr --prefix-address --show-raw-insn\n"
+ "#name: Maverick\n"
+ "#as: -marm9e\n"
+ "\n"
+ "# Test the instructions of Maverick\n"
+ "\n"
+ ".*: +file format.*arm.*\n"
+ "\n"
+ "Disassembly of section .text:\n",
+ dis_out);
+
+ /* Now emit all (selected) insns. */
+ output_groups (groups, as_in, dis_out);
+
+ exit (0);
+ }
*** /dev/null Sat Mar 24 00:37:44 2001
--- maverick.s Mon Oct 8 13:10:18 2001
***************
*** 0 ****
--- 1,470 ----
+ .text
+ .align
+ load_store:
+ cfldrseq mvf5, [sp, #255]
+ cfldrsmi mvf14, [r11, #73]
+ cfldrsvc mvf2, [r12, #-239]
+ cfldrslt mvf0, [r10, #-255]
+ cfldrscc mvf12, [r1, #-39]
+ cfldrs mvf13, [r15, #104]!
+ cfldrscs mvf9, [r0, #-0]!
+ cfldrsge mvf9, [lr, #72]!
+ cfldrshi mvf13, [r5, #37]!
+ cfldrsgt mvf6, [r3, #0]!
+ cfldrspl mvf14, [r4], #64
+ cfldrsne mvf8, [r2], #-157
+ cfldrslt mvf4, [r9], #1
+ cfldrspl mvf15, [r7], #-63
+ cfldrsal mvf3, [r8], #-136
+ cfldrdcs mvd1, [r6, #-68]
+ cfldrdeq mvd7, [r13, #255]
+ cfldrdgt mvd10, [r11, #73]
+ cfldrdle mvd6, [r12, #-239]
+ cfldrdls mvd0, [r10, #-255]
+ cfldrdls mvd4, [r1, #-39]!
+ cfldrdle mvd7, [pc, #104]!
+ cfldrdvs mvd11, [r0, #-0]!
+ cfldrdal mvd3, [r14, #72]!
+ cfldrdhi mvd15, [r5, #37]!
+ cfldrdmi mvd2, [r3], #0
+ cfldrd mvd10, [r4], #64
+ cfldrdcc mvd8, [r2], #-157
+ cfldrdne mvd12, [r9], #1
+ cfldrdvc mvd5, [r7], #-63
+ cfldr32ge mvfx1, [r8, #-136]
+ cfldr32vs mvfx11, [r6, #-68]
+ cfldr32eq mvfx5, [sp, #255]
+ cfldr32mi mvfx14, [r11, #73]
+ cfldr32vc mvfx2, [r12, #-239]
+ cfldr32lt mvfx0, [r10, #-255]!
+ cfldr32cc mvfx12, [r1, #-39]!
+ cfldr32 mvfx13, [r15, #104]!
+ cfldr32cs mvfx9, [r0, #-0]!
+ cfldr32ge mvfx9, [lr, #72]!
+ cfldr32hi mvfx13, [r5], #37
+ cfldr32gt mvfx6, [r3], #0
+ cfldr32pl mvfx14, [r4], #64
+ cfldr32ne mvfx8, [r2], #-157
+ cfldr32lt mvfx4, [r9], #1
+ cfldr64pl mvdx15, [r7, #-63]
+ cfldr64al mvdx3, [r8, #-136]
+ cfldr64cs mvdx1, [r6, #-68]
+ cfldr64eq mvdx7, [r13, #255]
+ cfldr64gt mvdx10, [r11, #73]
+ cfldr64le mvdx6, [r12, #-239]!
+ cfldr64ls mvdx0, [r10, #-255]!
+ cfldr64ls mvdx4, [r1, #-39]!
+ cfldr64le mvdx7, [pc, #104]!
+ cfldr64vs mvdx11, [r0, #-0]!
+ cfldr64al mvdx3, [r14], #72
+ cfldr64hi mvdx15, [r5], #37
+ cfldr64mi mvdx2, [r3], #0
+ cfldr64 mvdx10, [r4], #64
+ cfldr64cc mvdx8, [r2], #-157
+ cfstrsne mvf12, [r9, #1]
+ cfstrsvc mvf5, [r7, #-63]
+ cfstrsge mvf1, [r8, #-136]
+ cfstrsvs mvf11, [r6, #-68]
+ cfstrseq mvf5, [sp, #255]
+ cfstrsmi mvf14, [r11, #73]!
+ cfstrsvc mvf2, [r12, #-239]!
+ cfstrslt mvf0, [r10, #-255]!
+ cfstrscc mvf12, [r1, #-39]!
+ cfstrs mvf13, [r15, #104]!
+ cfstrscs mvf9, [r0], #-0
+ cfstrsge mvf9, [lr], #72
+ cfstrshi mvf13, [r5], #37
+ cfstrsgt mvf6, [r3], #0
+ cfstrspl mvf14, [r4], #64
+ cfstrdne mvd8, [r2, #-157]
+ cfstrdlt mvd4, [r9, #1]
+ cfstrdpl mvd15, [r7, #-63]
+ cfstrdal mvd3, [r8, #-136]
+ cfstrdcs mvd1, [r6, #-68]
+ cfstrdeq mvd7, [r13, #255]!
+ cfstrdgt mvd10, [r11, #73]!
+ cfstrdle mvd6, [r12, #-239]!
+ cfstrdls mvd0, [r10, #-255]!
+ cfstrdls mvd4, [r1, #-39]!
+ cfstrdle mvd7, [pc], #104
+ cfstrdvs mvd11, [r0], #-0
+ cfstrdal mvd3, [r14], #72
+ cfstrdhi mvd15, [r5], #37
+ cfstrdmi mvd2, [r3], #0
+ cfstr32 mvfx10, [r4, #64]
+ cfstr32cc mvfx8, [r2, #-157]
+ cfstr32ne mvfx12, [r9, #1]
+ cfstr32vc mvfx5, [r7, #-63]
+ cfstr32ge mvfx1, [r8, #-136]
+ cfstr32vs mvfx11, [r6, #-68]!
+ cfstr32eq mvfx5, [sp, #255]!
+ cfstr32mi mvfx14, [r11, #73]!
+ cfstr32vc mvfx2, [r12, #-239]!
+ cfstr32lt mvfx0, [r10, #-255]!
+ cfstr32cc mvfx12, [r1], #-39
+ cfstr32 mvfx13, [r15], #104
+ cfstr32cs mvfx9, [r0], #-0
+ cfstr32ge mvfx9, [lr], #72
+ cfstr32hi mvfx13, [r5], #37
+ cfstr64gt mvdx6, [r3, #0]
+ cfstr64pl mvdx14, [r4, #64]
+ cfstr64ne mvdx8, [r2, #-157]
+ cfstr64lt mvdx4, [r9, #1]
+ cfstr64pl mvdx15, [r7, #-63]
+ cfstr64al mvdx3, [r8, #-136]!
+ cfstr64cs mvdx1, [r6, #-68]!
+ cfstr64eq mvdx7, [r13, #255]!
+ cfstr64gt mvdx10, [r11, #73]!
+ cfstr64le mvdx6, [r12, #-239]!
+ cfstr64ls mvdx0, [r10], #-255
+ cfstr64ls mvdx4, [r1], #-39
+ cfstr64le mvdx7, [pc], #104
+ cfstr64vs mvdx11, [r0], #-0
+ cfstr64al mvdx3, [r14], #72
+ move:
+ cfmvsrhi mvf15, r5
+ cfmvsrvs mvf11, r6
+ cfmvsrcs mvf9, r0
+ cfmvsrpl mvf15, r7
+ cfmvsrls mvf4, r1
+ cfmvrscc r8, mvf13
+ cfmvrsvc pc, mvf1
+ cfmvrsgt r9, mvf11
+ cfmvrseq r10, mvf5
+ cfmvrsal r4, mvf12
+ cfmvdlrge mvd1, r8
+ cfmvdlr mvd13, r15
+ cfmvdlrlt mvd4, r9
+ cfmvdlrls mvd0, r10
+ cfmvdlr mvd10, r4
+ cfmvrdlmi r1, mvd3
+ cfmvrdlhi r2, mvd7
+ cfmvrdlcs r12, mvd12
+ cfmvrdlvs r3, mvd0
+ cfmvrdlvc r13, mvd14
+ cfmvdhrcc mvd12, r1
+ cfmvdhrne mvd8, r2
+ cfmvdhrle mvd6, r12
+ cfmvdhrmi mvd2, r3
+ cfmvdhreq mvd5, sp
+ cfmvrdhge r4, mvd4
+ cfmvrdhal r11, mvd8
+ cfmvrdhle r5, mvd2
+ cfmvrdhne r6, mvd6
+ cfmvrdhlt r0, mvd7
+ cfmv64lrpl mvdx14, r4
+ cfmv64lrgt mvdx10, r11
+ cfmv64lrhi mvdx15, r5
+ cfmv64lrvs mvdx11, r6
+ cfmv64lrcs mvdx9, r0
+ cfmvr64lpl sp, mvdx10
+ cfmvr64lls lr, mvdx14
+ cfmvr64lcc r8, mvdx13
+ cfmvr64lvc pc, mvdx1
+ cfmvr64lgt r9, mvdx11
+ cfmv64hreq mvdx7, r13
+ cfmv64hral mvdx3, r14
+ cfmv64hrge mvdx1, r8
+ cfmv64hr mvdx13, r15
+ cfmv64hrlt mvdx4, r9
+ cfmvr64hls r0, mvdx5
+ cfmvr64h r7, mvdx9
+ cfmvr64hmi r1, mvdx3
+ cfmvr64hhi r2, mvdx7
+ cfmvr64hcs r12, mvdx12
+ cfmval32vs mvax1, mvfx0
+ cfmval32vc mvax3, mvfx14
+ cfmval32cc mvax0, mvfx10
+ cfmval32ne mvax1, mvfx15
+ cfmval32le mvax0, mvfx11
+ cfmv32almi mvfx2, mvax1
+ cfmv32aleq mvfx5, mvax3
+ cfmv32alge mvfx9, mvax0
+ cfmv32alal mvfx3, mvax1
+ cfmv32alle mvfx7, mvax0
+ cfmvam32ne mvax2, mvfx6
+ cfmvam32lt mvax0, mvfx7
+ cfmvam32pl mvax2, mvfx3
+ cfmvam32gt mvax1, mvfx1
+ cfmvam32hi mvax3, mvfx13
+ cfmv32amvs mvfx11, mvax2
+ cfmv32amcs mvfx9, mvax0
+ cfmv32ampl mvfx15, mvax2
+ cfmv32amls mvfx4, mvax1
+ cfmv32amcc mvfx8, mvax3
+ cfmvah32vc mvax0, mvfx1
+ cfmvah32gt mvax0, mvfx11
+ cfmvah32eq mvax1, mvfx5
+ cfmvah32al mvax2, mvfx12
+ cfmvah32ge mvax3, mvfx8
+ cfmv32ah mvfx13, mvax0
+ cfmv32ahlt mvfx4, mvax0
+ cfmv32ahls mvfx0, mvax1
+ cfmv32ah mvfx10, mvax2
+ cfmv32ahmi mvfx14, mvax3
+ cfmva32hi mvax3, mvfx7
+ cfmva32cs mvax3, mvfx12
+ cfmva32vs mvax1, mvfx0
+ cfmva32vc mvax3, mvfx14
+ cfmva32cc mvax0, mvfx10
+ cfmv32ane mvfx8, mvax3
+ cfmv32ale mvfx6, mvax3
+ cfmv32ami mvfx2, mvax1
+ cfmv32aeq mvfx5, mvax3
+ cfmv32age mvfx9, mvax0
+ cfmva64al mvax3, mvdx8
+ cfmva64le mvax2, mvdx2
+ cfmva64ne mvax2, mvdx6
+ cfmva64lt mvax0, mvdx7
+ cfmva64pl mvax2, mvdx3
+ cfmv64agt mvdx10, mvax3
+ cfmv64ahi mvdx15, mvax2
+ cfmv64avs mvdx11, mvax2
+ cfmv64acs mvdx9, mvax0
+ cfmv64apl mvdx15, mvax2
+ cfmvsc32ls dspsc, mvfx14
+ cfmvsc32cc dspsc, mvfx13
+ cfmvsc32vc dspsc, mvfx1
+ cfmvsc32gt dspsc, mvfx11
+ cfmvsc32eq dspsc, mvfx5
+ cfmv32scal mvfx3, dspsc
+ cfmv32scge mvfx1, dspsc
+ cfmv32sc mvfx13, dspsc
+ cfmv32sclt mvfx4, dspsc
+ cfmv32scls mvfx0, dspsc
+ cfcpys mvf10, mvf9
+ cfcpysmi mvf14, mvf3
+ cfcpyshi mvf13, mvf7
+ cfcpyscs mvf1, mvf12
+ cfcpysvs mvf11, mvf0
+ cfcpydvc mvd5, mvd14
+ cfcpydcc mvd12, mvd10
+ cfcpydne mvd8, mvd15
+ cfcpydle mvd6, mvd11
+ cfcpydmi mvd2, mvd9
+ conv:
+ cfcvtsdeq mvd5, mvf15
+ cfcvtsdge mvd9, mvf4
+ cfcvtsdal mvd3, mvf8
+ cfcvtsdle mvd7, mvf2
+ cfcvtsdne mvd12, mvf6
+ cfcvtdslt mvf0, mvd7
+ cfcvtdspl mvf14, mvd3
+ cfcvtdsgt mvf10, mvd1
+ cfcvtdshi mvf15, mvd13
+ cfcvtdsvs mvf11, mvd4
+ cfcvt32scs mvf9, mvfx0
+ cfcvt32spl mvf15, mvfx10
+ cfcvt32sls mvf4, mvfx14
+ cfcvt32scc mvf8, mvfx13
+ cfcvt32svc mvf2, mvfx1
+ cfcvt32dgt mvd6, mvfx11
+ cfcvt32deq mvd7, mvfx5
+ cfcvt32dal mvd3, mvfx12
+ cfcvt32dge mvd1, mvfx8
+ cfcvt32d mvd13, mvfx6
+ cfcvt64slt mvf4, mvdx2
+ cfcvt64sls mvf0, mvdx5
+ cfcvt64s mvf10, mvdx9
+ cfcvt64smi mvf14, mvdx3
+ cfcvt64shi mvf13, mvdx7
+ cfcvt64dcs mvd1, mvdx12
+ cfcvt64dvs mvd11, mvdx0
+ cfcvt64dvc mvd5, mvdx14
+ cfcvt64dcc mvd12, mvdx10
+ cfcvt64dne mvd8, mvdx15
+ cfcvts32le mvfx6, mvf11
+ cfcvts32mi mvfx2, mvf9
+ cfcvts32eq mvfx5, mvf15
+ cfcvts32ge mvfx9, mvf4
+ cfcvts32al mvfx3, mvf8
+ cfcvtd32le mvfx7, mvd2
+ cfcvtd32ne mvfx12, mvd6
+ cfcvtd32lt mvfx0, mvd7
+ cfcvtd32pl mvfx14, mvd3
+ cfcvtd32gt mvfx10, mvd1
+ cftruncs32hi mvfx15, mvf13
+ cftruncs32vs mvfx11, mvf4
+ cftruncs32cs mvfx9, mvf0
+ cftruncs32pl mvfx15, mvf10
+ cftruncs32ls mvfx4, mvf14
+ cftruncd32cc mvfx8, mvd13
+ cftruncd32vc mvfx2, mvd1
+ cftruncd32gt mvfx6, mvd11
+ cftruncd32eq mvfx7, mvd5
+ cftruncd32al mvfx3, mvd12
+ shift:
+ cfrshl32ge mvfx1, mvfx8, r2
+ cfrshl32vs mvfx11, mvfx4, r9
+ cfrshl32eq mvfx5, mvfx15, r7
+ cfrshl32mi mvfx14, mvfx3, r8
+ cfrshl32vc mvfx2, mvfx1, r6
+ cfrshl64lt mvdx0, mvdx7, r13
+ cfrshl64cc mvdx12, mvdx10, r11
+ cfrshl64 mvdx13, mvdx6, r12
+ cfrshl64cs mvdx9, mvdx0, r10
+ cfrshl64ge mvdx9, mvdx4, r1
+ cfsh32hi mvfx13, mvfx7, #33
+ cfsh32gt mvfx6, mvfx11, #0
+ cfsh32pl mvfx14, mvfx3, #32
+ cfsh32ne mvfx8, mvfx15, #-31
+ cfsh32lt mvfx4, mvfx2, #1
+ cfsh64pl mvdx15, mvdx10, #-32
+ cfsh64al mvdx3, mvdx8, #-27
+ cfsh64cs mvdx1, mvdx12, #-5
+ cfsh64eq mvdx7, mvdx5, #63
+ cfsh64gt mvdx10, mvdx1, #9
+ comp:
+ cfcmpsle r15, mvf11, mvf4
+ cfcmpsls r0, mvf5, mvf15
+ cfcmpsls lr, mvf14, mvf3
+ cfcmpsle r5, mvf2, mvf1
+ cfcmpsvs r3, mvf0, mvf7
+ cfcmpdal r4, mvd12, mvd10
+ cfcmpdhi r2, mvd13, mvd6
+ cfcmpdmi r9, mvd9, mvd0
+ cfcmpd r7, mvd9, mvd4
+ cfcmpdcc r8, mvd13, mvd7
+ cfcmp32ne r6, mvfx6, mvfx11
+ cfcmp32vc r13, mvfx14, mvfx3
+ cfcmp32ge r11, mvfx8, mvfx15
+ cfcmp32vs r12, mvfx4, mvfx2
+ cfcmp32eq r10, mvfx15, mvfx10
+ cfcmp64mi r1, mvdx3, mvdx8
+ cfcmp64vc pc, mvdx1, mvdx12
+ cfcmp64lt r0, mvdx7, mvdx5
+ cfcmp64cc r14, mvdx10, mvdx1
+ cfcmp64 r5, mvdx6, mvdx11
+ fp_arith:
+ cfabsscs mvf9, mvf0
+ cfabsspl mvf15, mvf10
+ cfabssls mvf4, mvf14
+ cfabsscc mvf8, mvf13
+ cfabssvc mvf2, mvf1
+ cfabsdgt mvd6, mvd11
+ cfabsdeq mvd7, mvd5
+ cfabsdal mvd3, mvd12
+ cfabsdge mvd1, mvd8
+ cfabsd mvd13, mvd6
+ cfnegslt mvf4, mvf2
+ cfnegsls mvf0, mvf5
+ cfnegs mvf10, mvf9
+ cfnegsmi mvf14, mvf3
+ cfnegshi mvf13, mvf7
+ cfnegdcs mvd1, mvd12
+ cfnegdvs mvd11, mvd0
+ cfnegdvc mvd5, mvd14
+ cfnegdcc mvd12, mvd10
+ cfnegdne mvd8, mvd15
+ cfaddsle mvf6, mvf11, mvf4
+ cfaddsls mvf0, mvf5, mvf15
+ cfaddsls mvf4, mvf14, mvf3
+ cfaddsle mvf7, mvf2, mvf1
+ cfaddsvs mvf11, mvf0, mvf7
+ cfadddal mvd3, mvd12, mvd10
+ cfadddhi mvd15, mvd13, mvd6
+ cfadddmi mvd2, mvd9, mvd0
+ cfaddd mvd10, mvd9, mvd4
+ cfadddcc mvd8, mvd13, mvd7
+ cfsubsne mvf12, mvf6, mvf11
+ cfsubsvc mvf5, mvf14, mvf3
+ cfsubsge mvf1, mvf8, mvf15
+ cfsubsvs mvf11, mvf4, mvf2
+ cfsubseq mvf5, mvf15, mvf10
+ cfsubdmi mvd14, mvd3, mvd8
+ cfsubdvc mvd2, mvd1, mvd12
+ cfsubdlt mvd0, mvd7, mvd5
+ cfsubdcc mvd12, mvd10, mvd1
+ cfsubd mvd13, mvd6, mvd11
+ cfmulscs mvf9, mvf0, mvf5
+ cfmulsge mvf9, mvf4, mvf14
+ cfmulshi mvf13, mvf7, mvf2
+ cfmulsgt mvf6, mvf11, mvf0
+ cfmulspl mvf14, mvf3, mvf12
+ cfmuldne mvd8, mvd15, mvd13
+ cfmuldlt mvd4, mvd2, mvd9
+ cfmuldpl mvd15, mvd10, mvd9
+ cfmuldal mvd3, mvd8, mvd13
+ cfmuldcs mvd1, mvd12, mvd6
+ int_arith:
+ cfabs32eq mvfx7, mvfx5
+ cfabs32al mvfx3, mvfx12
+ cfabs32ge mvfx1, mvfx8
+ cfabs32 mvfx13, mvfx6
+ cfabs32lt mvfx4, mvfx2
+ cfabs64ls mvdx0, mvdx5
+ cfabs64 mvdx10, mvdx9
+ cfabs64mi mvdx14, mvdx3
+ cfabs64hi mvdx13, mvdx7
+ cfabs64cs mvdx1, mvdx12
+ cfneg32vs mvfx11, mvfx0
+ cfneg32vc mvfx5, mvfx14
+ cfneg32cc mvfx12, mvfx10
+ cfneg32ne mvfx8, mvfx15
+ cfneg32le mvfx6, mvfx11
+ cfneg64mi mvdx2, mvdx9
+ cfneg64eq mvdx5, mvdx15
+ cfneg64ge mvdx9, mvdx4
+ cfneg64al mvdx3, mvdx8
+ cfneg64le mvdx7, mvdx2
+ cfadd32ne mvfx12, mvfx6, mvfx11
+ cfadd32vc mvfx5, mvfx14, mvfx3
+ cfadd32ge mvfx1, mvfx8, mvfx15
+ cfadd32vs mvfx11, mvfx4, mvfx2
+ cfadd32eq mvfx5, mvfx15, mvfx10
+ cfadd64mi mvdx14, mvdx3, mvdx8
+ cfadd64vc mvdx2, mvdx1, mvdx12
+ cfadd64lt mvdx0, mvdx7, mvdx5
+ cfadd64cc mvdx12, mvdx10, mvdx1
+ cfadd64 mvdx13, mvdx6, mvdx11
+ cfsub32cs mvfx9, mvfx0, mvfx5
+ cfsub32ge mvfx9, mvfx4, mvfx14
+ cfsub32hi mvfx13, mvfx7, mvfx2
+ cfsub32gt mvfx6, mvfx11, mvfx0
+ cfsub32pl mvfx14, mvfx3, mvfx12
+ cfsub64ne mvdx8, mvdx15, mvdx13
+ cfsub64lt mvdx4, mvdx2, mvdx9
+ cfsub64pl mvdx15, mvdx10, mvdx9
+ cfsub64al mvdx3, mvdx8, mvdx13
+ cfsub64cs mvdx1, mvdx12, mvdx6
+ cfmul32eq mvfx7, mvfx5, mvfx14
+ cfmul32gt mvfx10, mvfx1, mvfx8
+ cfmul32le mvfx6, mvfx11, mvfx4
+ cfmul32ls mvfx0, mvfx5, mvfx15
+ cfmul32ls mvfx4, mvfx14, mvfx3
+ cfmul64le mvdx7, mvdx2, mvdx1
+ cfmul64vs mvdx11, mvdx0, mvdx7
+ cfmul64al mvdx3, mvdx12, mvdx10
+ cfmul64hi mvdx15, mvdx13, mvdx6
+ cfmul64mi mvdx2, mvdx9, mvdx0
+ cfmac32 mvfx10, mvfx9, mvfx4
+ cfmac32cc mvfx8, mvfx13, mvfx7
+ cfmac32ne mvfx12, mvfx6, mvfx11
+ cfmac32vc mvfx5, mvfx14, mvfx3
+ cfmac32ge mvfx1, mvfx8, mvfx15
+ cfmsc32vs mvfx11, mvfx4, mvfx2
+ cfmsc32eq mvfx5, mvfx15, mvfx10
+ cfmsc32mi mvfx14, mvfx3, mvfx8
+ cfmsc32vc mvfx2, mvfx1, mvfx12
+ cfmsc32lt mvfx0, mvfx7, mvfx5
+ acc_arith:
+ cfmadd32cc mvax0, mvfx10, mvfx1, mvfx8
+ cfmadd32 mvax2, mvfx6, mvfx11, mvfx4
+ cfmadd32cs mvax1, mvfx0, mvfx5, mvfx15
+ cfmadd32ge mvax2, mvfx4, mvfx14, mvfx3
+ cfmadd32hi mvax3, mvfx7, mvfx2, mvfx1
+ cfmsub32gt mvax0, mvfx11, mvfx0, mvfx7
+ cfmsub32pl mvax2, mvfx3, mvfx12, mvfx10
+ cfmsub32ne mvax1, mvfx15, mvfx13, mvfx6
+ cfmsub32lt mvax2, mvfx2, mvfx9, mvfx0
+ cfmsub32pl mvax3, mvfx10, mvfx9, mvfx4
+ cfmadda32al mvax3, mvax1, mvfx13, mvfx7
+ cfmadda32cs mvax3, mvax2, mvfx6, mvfx11
+ cfmadda32eq mvax1, mvax3, mvfx14, mvfx3
+ cfmadda32gt mvax1, mvax3, mvfx8, mvfx15
+ cfmadda32le mvax0, mvax3, mvfx4, mvfx2
+ cfmsuba32ls mvax0, mvax1, mvfx15, mvfx10
+ cfmsuba32ls mvax0, mvax1, mvfx3, mvfx8
+ cfmsuba32le mvax2, mvax0, mvfx1, mvfx12
+ cfmsuba32vs mvax1, mvax0, mvfx7, mvfx5
+ cfmsuba32al mvax2, mvax0, mvfx10, mvfx1
*** /dev/null Sat Mar 24 00:37:44 2001
--- maverick.d Mon Oct 8 13:10:18 2001
***************
*** 0 ****
--- 1,477 ----
+ #objdump: -dr --prefix-address --show-raw-insn
+ #name: Maverick
+ #as: -marm9e
+
+ # Test the instructions of Maverick
+
+ .*: +file format.*arm.*
+
+ Disassembly of section .text:
+ # load_store:
+ 00000000 <load_store> 0d ?9d ?54 ?ff ? * cfldrseq mvf5, ?\[sp, ?#255\]
+ 00000004 <load_store\+0x4> 4d ?9b ?e4 ?49 ? * cfldrsmi mvf14, ?\[r11, ?#73\]
+ 00000008 <load_store\+0x8> 7d ?1c ?24 ?ef ? * cfldrsvc mvf2, ?\[r12, ?#-239\]
+ 0000000c <load_store\+0xc> bd ?1a ?04 ?ff ? * cfldrslt mvf0, ?\[r10, ?#-255\]
+ 00000010 <load_store\+0x10> 3d ?11 ?c4 ?27 ? * cfldrscc mvf12, ?\[r1, ?#-39\]
+ 00000014 <load_store\+0x14> ed ?bf ?d4 ?68 ? * cfldrs mvf13, ?\[pc, ?#104\]!
+ 00000018 <load_store\+0x18> 2d ?30 ?94 ?00 ? * cfldrscs mvf9, ?\[r0, ?#-0\]!
+ 0000001c <load_store\+0x1c> ad ?be ?94 ?48 ? * cfldrsge mvf9, ?\[lr, ?#72\]!
+ 00000020 <load_store\+0x20> 8d ?b5 ?d4 ?25 ? * cfldrshi mvf13, ?\[r5, ?#37\]!
+ 00000024 <load_store\+0x24> cd ?b3 ?64 ?00 ? * cfldrsgt mvf6, ?\[r3, ?#0\]!
+ 00000028 <load_store\+0x28> 5c ?94 ?e4 ?40 ? * cfldrspl mvf14, ?\[r4\], ?#64
+ 0000002c <load_store\+0x2c> 1c ?12 ?84 ?9d ? * cfldrsne mvf8, ?\[r2\], ?#-157
+ 00000030 <load_store\+0x30> bc ?99 ?44 ?01 ? * cfldrslt mvf4, ?\[r9\], ?#1
+ 00000034 <load_store\+0x34> 5c ?17 ?f4 ?3f ? * cfldrspl mvf15, ?\[r7\], ?#-63
+ 00000038 <load_store\+0x38> ec ?18 ?34 ?88 ? * cfldrs mvf3, ?\[r8\], ?#-136
+ 0000003c <load_store\+0x3c> 2d ?56 ?14 ?44 ? * cfldrdcs mvd1, ?\[r6, ?#-68\]
+ 00000040 <load_store\+0x40> 0d ?dd ?74 ?ff ? * cfldrdeq mvd7, ?\[sp, ?#255\]
+ 00000044 <load_store\+0x44> cd ?db ?a4 ?49 ? * cfldrdgt mvd10, ?\[r11, ?#73\]
+ 00000048 <load_store\+0x48> dd ?5c ?64 ?ef ? * cfldrdle mvd6, ?\[r12, ?#-239\]
+ 0000004c <load_store\+0x4c> 9d ?5a ?04 ?ff ? * cfldrdls mvd0, ?\[r10, ?#-255\]
+ 00000050 <load_store\+0x50> 9d ?71 ?44 ?27 ? * cfldrdls mvd4, ?\[r1, ?#-39\]!
+ 00000054 <load_store\+0x54> dd ?ff ?74 ?68 ? * cfldrdle mvd7, ?\[pc, ?#104\]!
+ 00000058 <load_store\+0x58> 6d ?70 ?b4 ?00 ? * cfldrdvs mvd11, ?\[r0, ?#-0\]!
+ 0000005c <load_store\+0x5c> ed ?fe ?34 ?48 ? * cfldrd mvd3, ?\[lr, ?#72\]!
+ 00000060 <load_store\+0x60> 8d ?f5 ?f4 ?25 ? * cfldrdhi mvd15, ?\[r5, ?#37\]!
+ 00000064 <load_store\+0x64> 4c ?d3 ?24 ?00 ? * cfldrdmi mvd2, ?\[r3\], ?#0
+ 00000068 <load_store\+0x68> ec ?d4 ?a4 ?40 ? * cfldrd mvd10, ?\[r4\], ?#64
+ 0000006c <load_store\+0x6c> 3c ?52 ?84 ?9d ? * cfldrdcc mvd8, ?\[r2\], ?#-157
+ 00000070 <load_store\+0x70> 1c ?d9 ?c4 ?01 ? * cfldrdne mvd12, ?\[r9\], ?#1
+ 00000074 <load_store\+0x74> 7c ?57 ?54 ?3f ? * cfldrdvc mvd5, ?\[r7\], ?#-63
+ 00000078 <load_store\+0x78> ad ?18 ?15 ?88 ? * cfldr32ge mvfx1, ?\[r8, ?#-136\]
+ 0000007c <load_store\+0x7c> 6d ?16 ?b5 ?44 ? * cfldr32vs mvfx11, ?\[r6, ?#-68\]
+ 00000080 <load_store\+0x80> 0d ?9d ?55 ?ff ? * cfldr32eq mvfx5, ?\[sp, ?#255\]
+ 00000084 <load_store\+0x84> 4d ?9b ?e5 ?49 ? * cfldr32mi mvfx14, ?\[r11, ?#73\]
+ 00000088 <load_store\+0x88> 7d ?1c ?25 ?ef ? * cfldr32vc mvfx2, ?\[r12, ?#-239\]
+ 0000008c <load_store\+0x8c> bd ?3a ?05 ?ff ? * cfldr32lt mvfx0, ?\[r10, ?#-255\]!
+ 00000090 <load_store\+0x90> 3d ?31 ?c5 ?27 ? * cfldr32cc mvfx12, ?\[r1, ?#-39\]!
+ 00000094 <load_store\+0x94> ed ?bf ?d5 ?68 ? * cfldr32 mvfx13, ?\[pc, ?#104\]!
+ 00000098 <load_store\+0x98> 2d ?30 ?95 ?00 ? * cfldr32cs mvfx9, ?\[r0, ?#-0\]!
+ 0000009c <load_store\+0x9c> ad ?be ?95 ?48 ? * cfldr32ge mvfx9, ?\[lr, ?#72\]!
+ 000000a0 <load_store\+0xa0> 8c ?95 ?d5 ?25 ? * cfldr32hi mvfx13, ?\[r5\], ?#37
+ 000000a4 <load_store\+0xa4> cc ?93 ?65 ?00 ? * cfldr32gt mvfx6, ?\[r3\], ?#0
+ 000000a8 <load_store\+0xa8> 5c ?94 ?e5 ?40 ? * cfldr32pl mvfx14, ?\[r4\], ?#64
+ 000000ac <load_store\+0xac> 1c ?12 ?85 ?9d ? * cfldr32ne mvfx8, ?\[r2\], ?#-157
+ 000000b0 <load_store\+0xb0> bc ?99 ?45 ?01 ? * cfldr32lt mvfx4, ?\[r9\], ?#1
+ 000000b4 <load_store\+0xb4> 5d ?57 ?f5 ?3f ? * cfldr64pl mvdx15, ?\[r7, ?#-63\]
+ 000000b8 <load_store\+0xb8> ed ?58 ?35 ?88 ? * cfldr64 mvdx3, ?\[r8, ?#-136\]
+ 000000bc <load_store\+0xbc> 2d ?56 ?15 ?44 ? * cfldr64cs mvdx1, ?\[r6, ?#-68\]
+ 000000c0 <load_store\+0xc0> 0d ?dd ?75 ?ff ? * cfldr64eq mvdx7, ?\[sp, ?#255\]
+ 000000c4 <load_store\+0xc4> cd ?db ?a5 ?49 ? * cfldr64gt mvdx10, ?\[r11, ?#73\]
+ 000000c8 <load_store\+0xc8> dd ?7c ?65 ?ef ? * cfldr64le mvdx6, ?\[r12, ?#-239\]!
+ 000000cc <load_store\+0xcc> 9d ?7a ?05 ?ff ? * cfldr64ls mvdx0, ?\[r10, ?#-255\]!
+ 000000d0 <load_store\+0xd0> 9d ?71 ?45 ?27 ? * cfldr64ls mvdx4, ?\[r1, ?#-39\]!
+ 000000d4 <load_store\+0xd4> dd ?ff ?75 ?68 ? * cfldr64le mvdx7, ?\[pc, ?#104\]!
+ 000000d8 <load_store\+0xd8> 6d ?70 ?b5 ?00 ? * cfldr64vs mvdx11, ?\[r0, ?#-0\]!
+ 000000dc <load_store\+0xdc> ec ?de ?35 ?48 ? * cfldr64 mvdx3, ?\[lr\], ?#72
+ 000000e0 <load_store\+0xe0> 8c ?d5 ?f5 ?25 ? * cfldr64hi mvdx15, ?\[r5\], ?#37
+ 000000e4 <load_store\+0xe4> 4c ?d3 ?25 ?00 ? * cfldr64mi mvdx2, ?\[r3\], ?#0
+ 000000e8 <load_store\+0xe8> ec ?d4 ?a5 ?40 ? * cfldr64 mvdx10, ?\[r4\], ?#64
+ 000000ec <load_store\+0xec> 3c ?52 ?85 ?9d ? * cfldr64cc mvdx8, ?\[r2\], ?#-157
+ 000000f0 <load_store\+0xf0> 1d ?89 ?c4 ?01 ? * cfstrsne mvf12, ?\[r9, ?#1\]
+ 000000f4 <load_store\+0xf4> 7d ?07 ?54 ?3f ? * cfstrsvc mvf5, ?\[r7, ?#-63\]
+ 000000f8 <load_store\+0xf8> ad ?08 ?14 ?88 ? * cfstrsge mvf1, ?\[r8, ?#-136\]
+ 000000fc <load_store\+0xfc> 6d ?06 ?b4 ?44 ? * cfstrsvs mvf11, ?\[r6, ?#-68\]
+ 00000100 <load_store\+0x100> 0d ?8d ?54 ?ff ? * cfstrseq mvf5, ?\[sp, ?#255\]
+ 00000104 <load_store\+0x104> 4d ?ab ?e4 ?49 ? * cfstrsmi mvf14, ?\[r11, ?#73\]!
+ 00000108 <load_store\+0x108> 7d ?2c ?24 ?ef ? * cfstrsvc mvf2, ?\[r12, ?#-239\]!
+ 0000010c <load_store\+0x10c> bd ?2a ?04 ?ff ? * cfstrslt mvf0, ?\[r10, ?#-255\]!
+ 00000110 <load_store\+0x110> 3d ?21 ?c4 ?27 ? * cfstrscc mvf12, ?\[r1, ?#-39\]!
+ 00000114 <load_store\+0x114> ed ?af ?d4 ?68 ? * cfstrs mvf13, ?\[pc, ?#104\]!
+ 00000118 <load_store\+0x118> 2c ?00 ?94 ?00 ? * cfstrscs mvf9, ?\[r0\], ?#-0
+ 0000011c <load_store\+0x11c> ac ?8e ?94 ?48 ? * cfstrsge mvf9, ?\[lr\], ?#72
+ 00000120 <load_store\+0x120> 8c ?85 ?d4 ?25 ? * cfstrshi mvf13, ?\[r5\], ?#37
+ 00000124 <load_store\+0x124> cc ?83 ?64 ?00 ? * cfstrsgt mvf6, ?\[r3\], ?#0
+ 00000128 <load_store\+0x128> 5c ?84 ?e4 ?40 ? * cfstrspl mvf14, ?\[r4\], ?#64
+ 0000012c <load_store\+0x12c> 1d ?42 ?84 ?9d ? * cfstrdne mvd8, ?\[r2, ?#-157\]
+ 00000130 <load_store\+0x130> bd ?c9 ?44 ?01 ? * cfstrdlt mvd4, ?\[r9, ?#1\]
+ 00000134 <load_store\+0x134> 5d ?47 ?f4 ?3f ? * cfstrdpl mvd15, ?\[r7, ?#-63\]
+ 00000138 <load_store\+0x138> ed ?48 ?34 ?88 ? * cfstrd mvd3, ?\[r8, ?#-136\]
+ 0000013c <load_store\+0x13c> 2d ?46 ?14 ?44 ? * cfstrdcs mvd1, ?\[r6, ?#-68\]
+ 00000140 <load_store\+0x140> 0d ?ed ?74 ?ff ? * cfstrdeq mvd7, ?\[sp, ?#255\]!
+ 00000144 <load_store\+0x144> cd ?eb ?a4 ?49 ? * cfstrdgt mvd10, ?\[r11, ?#73\]!
+ 00000148 <load_store\+0x148> dd ?6c ?64 ?ef ? * cfstrdle mvd6, ?\[r12, ?#-239\]!
+ 0000014c <load_store\+0x14c> 9d ?6a ?04 ?ff ? * cfstrdls mvd0, ?\[r10, ?#-255\]!
+ 00000150 <load_store\+0x150> 9d ?61 ?44 ?27 ? * cfstrdls mvd4, ?\[r1, ?#-39\]!
+ 00000154 <load_store\+0x154> dc ?cf ?74 ?68 ? * cfstrdle mvd7, ?\[pc\], ?#104
+ 00000158 <load_store\+0x158> 6c ?40 ?b4 ?00 ? * cfstrdvs mvd11, ?\[r0\], ?#-0
+ 0000015c <load_store\+0x15c> ec ?ce ?34 ?48 ? * cfstrd mvd3, ?\[lr\], ?#72
+ 00000160 <load_store\+0x160> 8c ?c5 ?f4 ?25 ? * cfstrdhi mvd15, ?\[r5\], ?#37
+ 00000164 <load_store\+0x164> 4c ?c3 ?24 ?00 ? * cfstrdmi mvd2, ?\[r3\], ?#0
+ 00000168 <load_store\+0x168> ed ?84 ?a5 ?40 ? * cfstr32 mvfx10, ?\[r4, ?#64\]
+ 0000016c <load_store\+0x16c> 3d ?02 ?85 ?9d ? * cfstr32cc mvfx8, ?\[r2, ?#-157\]
+ 00000170 <load_store\+0x170> 1d ?89 ?c5 ?01 ? * cfstr32ne mvfx12, ?\[r9, ?#1\]
+ 00000174 <load_store\+0x174> 7d ?07 ?55 ?3f ? * cfstr32vc mvfx5, ?\[r7, ?#-63\]
+ 00000178 <load_store\+0x178> ad ?08 ?15 ?88 ? * cfstr32ge mvfx1, ?\[r8, ?#-136\]
+ 0000017c <load_store\+0x17c> 6d ?26 ?b5 ?44 ? * cfstr32vs mvfx11, ?\[r6, ?#-68\]!
+ 00000180 <load_store\+0x180> 0d ?ad ?55 ?ff ? * cfstr32eq mvfx5, ?\[sp, ?#255\]!
+ 00000184 <load_store\+0x184> 4d ?ab ?e5 ?49 ? * cfstr32mi mvfx14, ?\[r11, ?#73\]!
+ 00000188 <load_store\+0x188> 7d ?2c ?25 ?ef ? * cfstr32vc mvfx2, ?\[r12, ?#-239\]!
+ 0000018c <load_store\+0x18c> bd ?2a ?05 ?ff ? * cfstr32lt mvfx0, ?\[r10, ?#-255\]!
+ 00000190 <load_store\+0x190> 3c ?01 ?c5 ?27 ? * cfstr32cc mvfx12, ?\[r1\], ?#-39
+ 00000194 <load_store\+0x194> ec ?8f ?d5 ?68 ? * cfstr32 mvfx13, ?\[pc\], ?#104
+ 00000198 <load_store\+0x198> 2c ?00 ?95 ?00 ? * cfstr32cs mvfx9, ?\[r0\], ?#-0
+ 0000019c <load_store\+0x19c> ac ?8e ?95 ?48 ? * cfstr32ge mvfx9, ?\[lr\], ?#72
+ 000001a0 <load_store\+0x1a0> 8c ?85 ?d5 ?25 ? * cfstr32hi mvfx13, ?\[r5\], ?#37
+ 000001a4 <load_store\+0x1a4> cd ?c3 ?65 ?00 ? * cfstr64gt mvdx6, ?\[r3, ?#0\]
+ 000001a8 <load_store\+0x1a8> 5d ?c4 ?e5 ?40 ? * cfstr64pl mvdx14, ?\[r4, ?#64\]
+ 000001ac <load_store\+0x1ac> 1d ?42 ?85 ?9d ? * cfstr64ne mvdx8, ?\[r2, ?#-157\]
+ 000001b0 <load_store\+0x1b0> bd ?c9 ?45 ?01 ? * cfstr64lt mvdx4, ?\[r9, ?#1\]
+ 000001b4 <load_store\+0x1b4> 5d ?47 ?f5 ?3f ? * cfstr64pl mvdx15, ?\[r7, ?#-63\]
+ 000001b8 <load_store\+0x1b8> ed ?68 ?35 ?88 ? * cfstr64 mvdx3, ?\[r8, ?#-136\]!
+ 000001bc <load_store\+0x1bc> 2d ?66 ?15 ?44 ? * cfstr64cs mvdx1, ?\[r6, ?#-68\]!
+ 000001c0 <load_store\+0x1c0> 0d ?ed ?75 ?ff ? * cfstr64eq mvdx7, ?\[sp, ?#255\]!
+ 000001c4 <load_store\+0x1c4> cd ?eb ?a5 ?49 ? * cfstr64gt mvdx10, ?\[r11, ?#73\]!
+ 000001c8 <load_store\+0x1c8> dd ?6c ?65 ?ef ? * cfstr64le mvdx6, ?\[r12, ?#-239\]!
+ 000001cc <load_store\+0x1cc> 9c ?4a ?05 ?ff ? * cfstr64ls mvdx0, ?\[r10\], ?#-255
+ 000001d0 <load_store\+0x1d0> 9c ?41 ?45 ?27 ? * cfstr64ls mvdx4, ?\[r1\], ?#-39
+ 000001d4 <load_store\+0x1d4> dc ?cf ?75 ?68 ? * cfstr64le mvdx7, ?\[pc\], ?#104
+ 000001d8 <load_store\+0x1d8> 6c ?40 ?b5 ?00 ? * cfstr64vs mvdx11, ?\[r0\], ?#-0
+ 000001dc <load_store\+0x1dc> ec ?ce ?35 ?48 ? * cfstr64 mvdx3, ?\[lr\], ?#72
+ # move:
+ 000001e0 <move> 8e ?0f ?54 ?50 ? * cfmvsrhi mvf15, ?r5
+ 000001e4 <move\+0x4> 6e ?0b ?64 ?50 ? * cfmvsrvs mvf11, ?r6
+ 000001e8 <move\+0x8> 2e ?09 ?04 ?50 ? * cfmvsrcs mvf9, ?r0
+ 000001ec <move\+0xc> 5e ?0f ?74 ?50 ? * cfmvsrpl mvf15, ?r7
+ 000001f0 <move\+0x10> 9e ?04 ?14 ?50 ? * cfmvsrls mvf4, ?r1
+ 000001f4 <move\+0x14> 3e ?1d ?84 ?50 ? * cfmvrscc r8, ?mvf13
+ 000001f8 <move\+0x18> 7e ?11 ?f4 ?50 ? * cfmvrsvc pc, ?mvf1
+ 000001fc <move\+0x1c> ce ?1b ?94 ?50 ? * cfmvrsgt r9, ?mvf11
+ 00000200 <move\+0x20> 0e ?15 ?a4 ?50 ? * cfmvrseq r10, ?mvf5
+ 00000204 <move\+0x24> ee ?1c ?44 ?50 ? * cfmvrs r4, ?mvf12
+ 00000208 <move\+0x28> ae ?01 ?84 ?10 ? * cfmvdlrge mvd1, ?r8
+ 0000020c <move\+0x2c> ee ?0d ?f4 ?10 ? * cfmvdlr mvd13, ?pc
+ 00000210 <move\+0x30> be ?04 ?94 ?10 ? * cfmvdlrlt mvd4, ?r9
+ 00000214 <move\+0x34> 9e ?00 ?a4 ?10 ? * cfmvdlrls mvd0, ?r10
+ 00000218 <move\+0x38> ee ?0a ?44 ?10 ? * cfmvdlr mvd10, ?r4
+ 0000021c <move\+0x3c> 4e ?13 ?14 ?10 ? * cfmvrdlmi r1, ?mvd3
+ 00000220 <move\+0x40> 8e ?17 ?24 ?10 ? * cfmvrdlhi r2, ?mvd7
+ 00000224 <move\+0x44> 2e ?1c ?c4 ?10 ? * cfmvrdlcs r12, ?mvd12
+ 00000228 <move\+0x48> 6e ?10 ?34 ?10 ? * cfmvrdlvs r3, ?mvd0
+ 0000022c <move\+0x4c> 7e ?1e ?d4 ?10 ? * cfmvrdlvc sp, ?mvd14
+ 00000230 <move\+0x50> 3e ?0c ?14 ?30 ? * cfmvdhrcc mvd12, ?r1
+ 00000234 <move\+0x54> 1e ?08 ?24 ?30 ? * cfmvdhrne mvd8, ?r2
+ 00000238 <move\+0x58> de ?06 ?c4 ?30 ? * cfmvdhrle mvd6, ?r12
+ 0000023c <move\+0x5c> 4e ?02 ?34 ?30 ? * cfmvdhrmi mvd2, ?r3
+ 00000240 <move\+0x60> 0e ?05 ?d4 ?30 ? * cfmvdhreq mvd5, ?sp
+ 00000244 <move\+0x64> ae ?14 ?44 ?30 ? * cfmvrdhge r4, ?mvd4
+ 00000248 <move\+0x68> ee ?18 ?b4 ?30 ? * cfmvrdh r11, ?mvd8
+ 0000024c <move\+0x6c> de ?12 ?54 ?30 ? * cfmvrdhle r5, ?mvd2
+ 00000250 <move\+0x70> 1e ?16 ?64 ?30 ? * cfmvrdhne r6, ?mvd6
+ 00000254 <move\+0x74> be ?17 ?04 ?30 ? * cfmvrdhlt r0, ?mvd7
+ 00000258 <move\+0x78> 5e ?0e ?45 ?10 ? * cfmv64lrpl mvdx14, ?r4
+ 0000025c <move\+0x7c> ce ?0a ?b5 ?10 ? * cfmv64lrgt mvdx10, ?r11
+ 00000260 <move\+0x80> 8e ?0f ?55 ?10 ? * cfmv64lrhi mvdx15, ?r5
+ 00000264 <move\+0x84> 6e ?0b ?65 ?10 ? * cfmv64lrvs mvdx11, ?r6
+ 00000268 <move\+0x88> 2e ?09 ?05 ?10 ? * cfmv64lrcs mvdx9, ?r0
+ 0000026c <move\+0x8c> 5e ?1a ?d5 ?10 ? * cfmvr64lpl sp, ?mvdx10
+ 00000270 <move\+0x90> 9e ?1e ?e5 ?10 ? * cfmvr64lls lr, ?mvdx14
+ 00000274 <move\+0x94> 3e ?1d ?85 ?10 ? * cfmvr64lcc r8, ?mvdx13
+ 00000278 <move\+0x98> 7e ?11 ?f5 ?10 ? * cfmvr64lvc pc, ?mvdx1
+ 0000027c <move\+0x9c> ce ?1b ?95 ?10 ? * cfmvr64lgt r9, ?mvdx11
+ 00000280 <move\+0xa0> 0e ?07 ?d5 ?30 ? * cfmv64hreq mvdx7, ?sp
+ 00000284 <move\+0xa4> ee ?03 ?e5 ?30 ? * cfmv64hr mvdx3, ?lr
+ 00000288 <move\+0xa8> ae ?01 ?85 ?30 ? * cfmv64hrge mvdx1, ?r8
+ 0000028c <move\+0xac> ee ?0d ?f5 ?30 ? * cfmv64hr mvdx13, ?pc
+ 00000290 <move\+0xb0> be ?04 ?95 ?30 ? * cfmv64hrlt mvdx4, ?r9
+ 00000294 <move\+0xb4> 9e ?15 ?05 ?30 ? * cfmvr64hls r0, ?mvdx5
+ 00000298 <move\+0xb8> ee ?19 ?75 ?30 ? * cfmvr64h r7, ?mvdx9
+ 0000029c <move\+0xbc> 4e ?13 ?15 ?30 ? * cfmvr64hmi r1, ?mvdx3
+ 000002a0 <move\+0xc0> 8e ?17 ?25 ?30 ? * cfmvr64hhi r2, ?mvdx7
+ 000002a4 <move\+0xc4> 2e ?1c ?c5 ?30 ? * cfmvr64hcs r12, ?mvdx12
+ 000002a8 <move\+0xc8> 6e ?10 ?06 ?11 ? * cfmval32vs mvax1, ?mvfx0
+ 000002ac <move\+0xcc> 7e ?1e ?06 ?13 ? * cfmval32vc mvax3, ?mvfx14
+ 000002b0 <move\+0xd0> 3e ?1a ?06 ?10 ? * cfmval32cc mvax0, ?mvfx10
+ 000002b4 <move\+0xd4> 1e ?1f ?06 ?11 ? * cfmval32ne mvax1, ?mvfx15
+ 000002b8 <move\+0xd8> de ?1b ?06 ?10 ? * cfmval32le mvax0, ?mvfx11
+ 000002bc <move\+0xdc> 4e ?01 ?06 ?12 ? * cfmv32almi mvfx2, ?mvax1
+ 000002c0 <move\+0xe0> 0e ?03 ?06 ?15 ? * cfmv32aleq mvfx5, ?mvax3
+ 000002c4 <move\+0xe4> ae ?00 ?06 ?19 ? * cfmv32alge mvfx9, ?mvax0
+ 000002c8 <move\+0xe8> ee ?01 ?06 ?13 ? * cfmv32al mvfx3, ?mvax1
+ 000002cc <move\+0xec> de ?00 ?06 ?17 ? * cfmv32alle mvfx7, ?mvax0
+ 000002d0 <move\+0xf0> 1e ?16 ?06 ?32 ? * cfmvam32ne mvax2, ?mvfx6
+ 000002d4 <move\+0xf4> be ?17 ?06 ?30 ? * cfmvam32lt mvax0, ?mvfx7
+ 000002d8 <move\+0xf8> 5e ?13 ?06 ?32 ? * cfmvam32pl mvax2, ?mvfx3
+ 000002dc <move\+0xfc> ce ?11 ?06 ?31 ? * cfmvam32gt mvax1, ?mvfx1
+ 000002e0 <move\+0x100> 8e ?1d ?06 ?33 ? * cfmvam32hi mvax3, ?mvfx13
+ 000002e4 <move\+0x104> 6e ?02 ?06 ?3b ? * cfmv32amvs mvfx11, ?mvax2
+ 000002e8 <move\+0x108> 2e ?00 ?06 ?39 ? * cfmv32amcs mvfx9, ?mvax0
+ 000002ec <move\+0x10c> 5e ?02 ?06 ?3f ? * cfmv32ampl mvfx15, ?mvax2
+ 000002f0 <move\+0x110> 9e ?01 ?06 ?34 ? * cfmv32amls mvfx4, ?mvax1
+ 000002f4 <move\+0x114> 3e ?03 ?06 ?38 ? * cfmv32amcc mvfx8, ?mvax3
+ 000002f8 <move\+0x118> 7e ?11 ?06 ?50 ? * cfmvah32vc mvax0, ?mvfx1
+ 000002fc <move\+0x11c> ce ?1b ?06 ?50 ? * cfmvah32gt mvax0, ?mvfx11
+ 00000300 <move\+0x120> 0e ?15 ?06 ?51 ? * cfmvah32eq mvax1, ?mvfx5
+ 00000304 <move\+0x124> ee ?1c ?06 ?52 ? * cfmvah32 mvax2, ?mvfx12
+ 00000308 <move\+0x128> ae ?18 ?06 ?53 ? * cfmvah32ge mvax3, ?mvfx8
+ 0000030c <move\+0x12c> ee ?00 ?06 ?5d ? * cfmv32ah mvfx13, ?mvax0
+ 00000310 <move\+0x130> be ?00 ?06 ?54 ? * cfmv32ahlt mvfx4, ?mvax0
+ 00000314 <move\+0x134> 9e ?01 ?06 ?50 ? * cfmv32ahls mvfx0, ?mvax1
+ 00000318 <move\+0x138> ee ?02 ?06 ?5a ? * cfmv32ah mvfx10, ?mvax2
+ 0000031c <move\+0x13c> 4e ?03 ?06 ?5e ? * cfmv32ahmi mvfx14, ?mvax3
+ 00000320 <move\+0x140> 8e ?17 ?06 ?73 ? * cfmva32hi mvax3, ?mvfx7
+ 00000324 <move\+0x144> 2e ?1c ?06 ?73 ? * cfmva32cs mvax3, ?mvfx12
+ 00000328 <move\+0x148> 6e ?10 ?06 ?71 ? * cfmva32vs mvax1, ?mvfx0
+ 0000032c <move\+0x14c> 7e ?1e ?06 ?73 ? * cfmva32vc mvax3, ?mvfx14
+ 00000330 <move\+0x150> 3e ?1a ?06 ?70 ? * cfmva32cc mvax0, ?mvfx10
+ 00000334 <move\+0x154> 1e ?03 ?06 ?78 ? * cfmv32ane mvfx8, ?mvax3
+ 00000338 <move\+0x158> de ?03 ?06 ?76 ? * cfmv32ale mvfx6, ?mvax3
+ 0000033c <move\+0x15c> 4e ?01 ?06 ?72 ? * cfmv32ami mvfx2, ?mvax1
+ 00000340 <move\+0x160> 0e ?03 ?06 ?75 ? * cfmv32aeq mvfx5, ?mvax3
+ 00000344 <move\+0x164> ae ?00 ?06 ?79 ? * cfmv32age mvfx9, ?mvax0
+ 00000348 <move\+0x168> ee ?18 ?06 ?93 ? * cfmva64 mvax3, ?mvdx8
+ 0000034c <move\+0x16c> de ?12 ?06 ?92 ? * cfmva64le mvax2, ?mvdx2
+ 00000350 <move\+0x170> 1e ?16 ?06 ?92 ? * cfmva64ne mvax2, ?mvdx6
+ 00000354 <move\+0x174> be ?17 ?06 ?90 ? * cfmva64lt mvax0, ?mvdx7
+ 00000358 <move\+0x178> 5e ?13 ?06 ?92 ? * cfmva64pl mvax2, ?mvdx3
+ 0000035c <move\+0x17c> ce ?03 ?06 ?9a ? * cfmv64agt mvdx10, ?mvax3
+ 00000360 <move\+0x180> 8e ?02 ?06 ?9f ? * cfmv64ahi mvdx15, ?mvax2
+ 00000364 <move\+0x184> 6e ?02 ?06 ?9b ? * cfmv64avs mvdx11, ?mvax2
+ 00000368 <move\+0x188> 2e ?00 ?06 ?99 ? * cfmv64acs mvdx9, ?mvax0
+ 0000036c <move\+0x18c> 5e ?02 ?06 ?9f ? * cfmv64apl mvdx15, ?mvax2
+ 00000370 <move\+0x190> 9e ?1e ?06 ?b0 ? * cfmvsc32ls dspsc, ?mvfx14
+ 00000374 <move\+0x194> 3e ?1d ?06 ?b0 ? * cfmvsc32cc dspsc, ?mvfx13
+ 00000378 <move\+0x198> 7e ?11 ?06 ?b0 ? * cfmvsc32vc dspsc, ?mvfx1
+ 0000037c <move\+0x19c> ce ?1b ?06 ?b0 ? * cfmvsc32gt dspsc, ?mvfx11
+ 00000380 <move\+0x1a0> 0e ?15 ?06 ?b0 ? * cfmvsc32eq dspsc, ?mvfx5
+ 00000384 <move\+0x1a4> ee ?00 ?06 ?b3 ? * cfmv32sc mvfx3, ?dspsc
+ 00000388 <move\+0x1a8> ae ?00 ?06 ?b1 ? * cfmv32scge mvfx1, ?dspsc
+ 0000038c <move\+0x1ac> ee ?00 ?06 ?bd ? * cfmv32sc mvfx13, ?dspsc
+ 00000390 <move\+0x1b0> be ?00 ?06 ?b4 ? * cfmv32sclt mvfx4, ?dspsc
+ 00000394 <move\+0x1b4> 9e ?00 ?06 ?b0 ? * cfmv32scls mvfx0, ?dspsc
+ 00000398 <move\+0x1b8> ee ?09 ?a4 ?00 ? * cfcpys mvf10, ?mvf9
+ 0000039c <move\+0x1bc> 4e ?03 ?e4 ?00 ? * cfcpysmi mvf14, ?mvf3
+ 000003a0 <move\+0x1c0> 8e ?07 ?d4 ?00 ? * cfcpyshi mvf13, ?mvf7
+ 000003a4 <move\+0x1c4> 2e ?0c ?14 ?00 ? * cfcpyscs mvf1, ?mvf12
+ 000003a8 <move\+0x1c8> 6e ?00 ?b4 ?00 ? * cfcpysvs mvf11, ?mvf0
+ 000003ac <move\+0x1cc> 7e ?0e ?54 ?20 ? * cfcpydvc mvd5, ?mvd14
+ 000003b0 <move\+0x1d0> 3e ?0a ?c4 ?20 ? * cfcpydcc mvd12, ?mvd10
+ 000003b4 <move\+0x1d4> 1e ?0f ?84 ?20 ? * cfcpydne mvd8, ?mvd15
+ 000003b8 <move\+0x1d8> de ?0b ?64 ?20 ? * cfcpydle mvd6, ?mvd11
+ 000003bc <move\+0x1dc> 4e ?09 ?24 ?20 ? * cfcpydmi mvd2, ?mvd9
+ # conv:
+ 000003c0 <conv> 0e ?0f ?54 ?60 ? * cfcvtsdeq mvd5, ?mvf15
+ 000003c4 <conv\+0x4> ae ?04 ?94 ?60 ? * cfcvtsdge mvd9, ?mvf4
+ 000003c8 <conv\+0x8> ee ?08 ?34 ?60 ? * cfcvtsd mvd3, ?mvf8
+ 000003cc <conv\+0xc> de ?02 ?74 ?60 ? * cfcvtsdle mvd7, ?mvf2
+ 000003d0 <conv\+0x10> 1e ?06 ?c4 ?60 ? * cfcvtsdne mvd12, ?mvf6
+ 000003d4 <conv\+0x14> be ?07 ?04 ?40 ? * cfcvtdslt mvf0, ?mvd7
+ 000003d8 <conv\+0x18> 5e ?03 ?e4 ?40 ? * cfcvtdspl mvf14, ?mvd3
+ 000003dc <conv\+0x1c> ce ?01 ?a4 ?40 ? * cfcvtdsgt mvf10, ?mvd1
+ 000003e0 <conv\+0x20> 8e ?0d ?f4 ?40 ? * cfcvtdshi mvf15, ?mvd13
+ 000003e4 <conv\+0x24> 6e ?04 ?b4 ?40 ? * cfcvtdsvs mvf11, ?mvd4
+ 000003e8 <conv\+0x28> 2e ?00 ?94 ?80 ? * cfcvt32scs mvf9, ?mvfx0
+ 000003ec <conv\+0x2c> 5e ?0a ?f4 ?80 ? * cfcvt32spl mvf15, ?mvfx10
+ 000003f0 <conv\+0x30> 9e ?0e ?44 ?80 ? * cfcvt32sls mvf4, ?mvfx14
+ 000003f4 <conv\+0x34> 3e ?0d ?84 ?80 ? * cfcvt32scc mvf8, ?mvfx13
+ 000003f8 <conv\+0x38> 7e ?01 ?24 ?80 ? * cfcvt32svc mvf2, ?mvfx1
+ 000003fc <conv\+0x3c> ce ?0b ?64 ?a0 ? * cfcvt32dgt mvd6, ?mvfx11
+ 00000400 <conv\+0x40> 0e ?05 ?74 ?a0 ? * cfcvt32deq mvd7, ?mvfx5
+ 00000404 <conv\+0x44> ee ?0c ?34 ?a0 ? * cfcvt32d mvd3, ?mvfx12
+ 00000408 <conv\+0x48> ae ?08 ?14 ?a0 ? * cfcvt32dge mvd1, ?mvfx8
+ 0000040c <conv\+0x4c> ee ?06 ?d4 ?a0 ? * cfcvt32d mvd13, ?mvfx6
+ 00000410 <conv\+0x50> be ?02 ?44 ?c0 ? * cfcvt64slt mvf4, ?mvdx2
+ 00000414 <conv\+0x54> 9e ?05 ?04 ?c0 ? * cfcvt64sls mvf0, ?mvdx5
+ 00000418 <conv\+0x58> ee ?09 ?a4 ?c0 ? * cfcvt64s mvf10, ?mvdx9
+ 0000041c <conv\+0x5c> 4e ?03 ?e4 ?c0 ? * cfcvt64smi mvf14, ?mvdx3
+ 00000420 <conv\+0x60> 8e ?07 ?d4 ?c0 ? * cfcvt64shi mvf13, ?mvdx7
+ 00000424 <conv\+0x64> 2e ?0c ?14 ?e0 ? * cfcvt64dcs mvd1, ?mvdx12
+ 00000428 <conv\+0x68> 6e ?00 ?b4 ?e0 ? * cfcvt64dvs mvd11, ?mvdx0
+ 0000042c <conv\+0x6c> 7e ?0e ?54 ?e0 ? * cfcvt64dvc mvd5, ?mvdx14
+ 00000430 <conv\+0x70> 3e ?0a ?c4 ?e0 ? * cfcvt64dcc mvd12, ?mvdx10
+ 00000434 <conv\+0x74> 1e ?0f ?84 ?e0 ? * cfcvt64dne mvd8, ?mvdx15
+ 00000438 <conv\+0x78> de ?1b ?65 ?80 ? * cfcvts32le mvfx6, ?mvf11
+ 0000043c <conv\+0x7c> 4e ?19 ?25 ?80 ? * cfcvts32mi mvfx2, ?mvf9
+ 00000440 <conv\+0x80> 0e ?1f ?55 ?80 ? * cfcvts32eq mvfx5, ?mvf15
+ 00000444 <conv\+0x84> ae ?14 ?95 ?80 ? * cfcvts32ge mvfx9, ?mvf4
+ 00000448 <conv\+0x88> ee ?18 ?35 ?80 ? * cfcvts32 mvfx3, ?mvf8
+ 0000044c <conv\+0x8c> de ?12 ?75 ?a0 ? * cfcvtd32le mvfx7, ?mvd2
+ 00000450 <conv\+0x90> 1e ?16 ?c5 ?a0 ? * cfcvtd32ne mvfx12, ?mvd6
+ 00000454 <conv\+0x94> be ?17 ?05 ?a0 ? * cfcvtd32lt mvfx0, ?mvd7
+ 00000458 <conv\+0x98> 5e ?13 ?e5 ?a0 ? * cfcvtd32pl mvfx14, ?mvd3
+ 0000045c <conv\+0x9c> ce ?11 ?a5 ?a0 ? * cfcvtd32gt mvfx10, ?mvd1
+ 00000460 <conv\+0xa0> 8e ?1d ?f5 ?c0 ? * cftruncs32hi mvfx15, ?mvf13
+ 00000464 <conv\+0xa4> 6e ?14 ?b5 ?c0 ? * cftruncs32vs mvfx11, ?mvf4
+ 00000468 <conv\+0xa8> 2e ?10 ?95 ?c0 ? * cftruncs32cs mvfx9, ?mvf0
+ 0000046c <conv\+0xac> 5e ?1a ?f5 ?c0 ? * cftruncs32pl mvfx15, ?mvf10
+ 00000470 <conv\+0xb0> 9e ?1e ?45 ?c0 ? * cftruncs32ls mvfx4, ?mvf14
+ 00000474 <conv\+0xb4> 3e ?1d ?85 ?e0 ? * cftruncd32cc mvfx8, ?mvd13
+ 00000478 <conv\+0xb8> 7e ?11 ?25 ?e0 ? * cftruncd32vc mvfx2, ?mvd1
+ 0000047c <conv\+0xbc> ce ?1b ?65 ?e0 ? * cftruncd32gt mvfx6, ?mvd11
+ 00000480 <conv\+0xc0> 0e ?15 ?75 ?e0 ? * cftruncd32eq mvfx7, ?mvd5
+ 00000484 <conv\+0xc4> ee ?1c ?35 ?e0 ? * cftruncd32 mvfx3, ?mvd12
+ # shift:
+ 00000488 <shift> ae ?01 ?25 ?58 ? * cfrshl32ge mvfx1, ?mvfx8, ?r2
+ 0000048c <shift\+0x4> 6e ?0b ?95 ?54 ? * cfrshl32vs mvfx11, ?mvfx4, ?r9
+ 00000490 <shift\+0x8> 0e ?05 ?75 ?5f ? * cfrshl32eq mvfx5, ?mvfx15, ?r7
+ 00000494 <shift\+0xc> 4e ?0e ?85 ?53 ? * cfrshl32mi mvfx14, ?mvfx3, ?r8
+ 00000498 <shift\+0x10> 7e ?02 ?65 ?51 ? * cfrshl32vc mvfx2, ?mvfx1, ?r6
+ 0000049c <shift\+0x14> be ?00 ?d5 ?77 ? * cfrshl64lt mvdx0, ?mvdx7, ?sp
+ 000004a0 <shift\+0x18> 3e ?0c ?b5 ?7a ? * cfrshl64cc mvdx12, ?mvdx10, ?r11
+ 000004a4 <shift\+0x1c> ee ?0d ?c5 ?76 ? * cfrshl64 mvdx13, ?mvdx6, ?r12
+ 000004a8 <shift\+0x20> 2e ?09 ?a5 ?70 ? * cfrshl64cs mvdx9, ?mvdx0, ?r10
+ 000004ac <shift\+0x24> ae ?09 ?15 ?74 ? * cfrshl64ge mvdx9, ?mvdx4, ?r1
+ 000004b0 <shift\+0x28> 8e ?07 ?d5 ?41 ? * cfsh32hi mvfx13, ?mvfx7, ?#33
+ 000004b4 <shift\+0x2c> ce ?0b ?65 ?00 ? * cfsh32gt mvfx6, ?mvfx11, ?#0
+ 000004b8 <shift\+0x30> 5e ?03 ?e5 ?40 ? * cfsh32pl mvfx14, ?mvfx3, ?#32
+ 000004bc <shift\+0x34> 1e ?0f ?85 ?c1 ? * cfsh32ne mvfx8, ?mvfx15, ?#-31
+ 000004c0 <shift\+0x38> be ?02 ?45 ?01 ? * cfsh32lt mvfx4, ?mvfx2, ?#1
+ 000004c4 <shift\+0x3c> 5e ?2a ?f5 ?c0 ? * cfsh64pl mvdx15, ?mvdx10, ?#-32
+ 000004c8 <shift\+0x40> ee ?28 ?35 ?c5 ? * cfsh64 mvdx3, ?mvdx8, ?#-27
+ 000004cc <shift\+0x44> 2e ?2c ?15 ?eb ? * cfsh64cs mvdx1, ?mvdx12, ?#-5
+ 000004d0 <shift\+0x48> 0e ?25 ?75 ?6f ? * cfsh64eq mvdx7, ?mvdx5, ?#63
+ 000004d4 <shift\+0x4c> ce ?21 ?a5 ?09 ? * cfsh64gt mvdx10, ?mvdx1, ?#9
+ # comp:
+ 000004d8 <comp> de ?1b ?f4 ?94 ? * cfcmpsle pc, ?mvf11, ?mvf4
+ 000004dc <comp\+0x4> 9e ?15 ?04 ?9f ? * cfcmpsls r0, ?mvf5, ?mvf15
+ 000004e0 <comp\+0x8> 9e ?1e ?e4 ?93 ? * cfcmpsls lr, ?mvf14, ?mvf3
+ 000004e4 <comp\+0xc> de ?12 ?54 ?91 ? * cfcmpsle r5, ?mvf2, ?mvf1
+ 000004e8 <comp\+0x10> 6e ?10 ?34 ?97 ? * cfcmpsvs r3, ?mvf0, ?mvf7
+ 000004ec <comp\+0x14> ee ?1c ?44 ?ba ? * cfcmpd r4, ?mvd12, ?mvd10
+ 000004f0 <comp\+0x18> 8e ?1d ?24 ?b6 ? * cfcmpdhi r2, ?mvd13, ?mvd6
+ 000004f4 <comp\+0x1c> 4e ?19 ?94 ?b0 ? * cfcmpdmi r9, ?mvd9, ?mvd0
+ 000004f8 <comp\+0x20> ee ?19 ?74 ?b4 ? * cfcmpd r7, ?mvd9, ?mvd4
+ 000004fc <comp\+0x24> 3e ?1d ?84 ?b7 ? * cfcmpdcc r8, ?mvd13, ?mvd7
+ 00000500 <comp\+0x28> 1e ?16 ?65 ?9b ? * cfcmp32ne r6, ?mvfx6, ?mvfx11
+ 00000504 <comp\+0x2c> 7e ?1e ?d5 ?93 ? * cfcmp32vc sp, ?mvfx14, ?mvfx3
+ 00000508 <comp\+0x30> ae ?18 ?b5 ?9f ? * cfcmp32ge r11, ?mvfx8, ?mvfx15
+ 0000050c <comp\+0x34> 6e ?14 ?c5 ?92 ? * cfcmp32vs r12, ?mvfx4, ?mvfx2
+ 00000510 <comp\+0x38> 0e ?1f ?a5 ?9a ? * cfcmp32eq r10, ?mvfx15, ?mvfx10
+ 00000514 <comp\+0x3c> 4e ?13 ?15 ?b8 ? * cfcmp64mi r1, ?mvdx3, ?mvdx8
+ 00000518 <comp\+0x40> 7e ?11 ?f5 ?bc ? * cfcmp64vc pc, ?mvdx1, ?mvdx12
+ 0000051c <comp\+0x44> be ?17 ?05 ?b5 ? * cfcmp64lt r0, ?mvdx7, ?mvdx5
+ 00000520 <comp\+0x48> 3e ?1a ?e5 ?b1 ? * cfcmp64cc lr, ?mvdx10, ?mvdx1
+ 00000524 <comp\+0x4c> ee ?16 ?55 ?bb ? * cfcmp64 r5, ?mvdx6, ?mvdx11
+ # fp_arith:
+ 00000528 <fp_arith> 2e ?30 ?94 ?00 ? * cfabsscs mvf9, ?mvf0
+ 0000052c <fp_arith\+0x4> 5e ?3a ?f4 ?00 ? * cfabsspl mvf15, ?mvf10
+ 00000530 <fp_arith\+0x8> 9e ?3e ?44 ?00 ? * cfabssls mvf4, ?mvf14
+ 00000534 <fp_arith\+0xc> 3e ?3d ?84 ?00 ? * cfabsscc mvf8, ?mvf13
+ 00000538 <fp_arith\+0x10> 7e ?31 ?24 ?00 ? * cfabssvc mvf2, ?mvf1
+ 0000053c <fp_arith\+0x14> ce ?3b ?64 ?20 ? * cfabsdgt mvd6, ?mvd11
+ 00000540 <fp_arith\+0x18> 0e ?35 ?74 ?20 ? * cfabsdeq mvd7, ?mvd5
+ 00000544 <fp_arith\+0x1c> ee ?3c ?34 ?20 ? * cfabsd mvd3, ?mvd12
+ 00000548 <fp_arith\+0x20> ae ?38 ?14 ?20 ? * cfabsdge mvd1, ?mvd8
+ 0000054c <fp_arith\+0x24> ee ?36 ?d4 ?20 ? * cfabsd mvd13, ?mvd6
+ 00000550 <fp_arith\+0x28> be ?32 ?44 ?40 ? * cfnegslt mvf4, ?mvf2
+ 00000554 <fp_arith\+0x2c> 9e ?35 ?04 ?40 ? * cfnegsls mvf0, ?mvf5
+ 00000558 <fp_arith\+0x30> ee ?39 ?a4 ?40 ? * cfnegs mvf10, ?mvf9
+ 0000055c <fp_arith\+0x34> 4e ?33 ?e4 ?40 ? * cfnegsmi mvf14, ?mvf3
+ 00000560 <fp_arith\+0x38> 8e ?37 ?d4 ?40 ? * cfnegshi mvf13, ?mvf7
+ 00000564 <fp_arith\+0x3c> 2e ?3c ?14 ?60 ? * cfnegdcs mvd1, ?mvd12
+ 00000568 <fp_arith\+0x40> 6e ?30 ?b4 ?60 ? * cfnegdvs mvd11, ?mvd0
+ 0000056c <fp_arith\+0x44> 7e ?3e ?54 ?60 ? * cfnegdvc mvd5, ?mvd14
+ 00000570 <fp_arith\+0x48> 3e ?3a ?c4 ?60 ? * cfnegdcc mvd12, ?mvd10
+ 00000574 <fp_arith\+0x4c> 1e ?3f ?84 ?60 ? * cfnegdne mvd8, ?mvd15
+ 00000578 <fp_arith\+0x50> de ?3b ?64 ?84 ? * cfaddsle mvf6, ?mvf11, ?mvf4
+ 0000057c <fp_arith\+0x54> 9e ?35 ?04 ?8f ? * cfaddsls mvf0, ?mvf5, ?mvf15
+ 00000580 <fp_arith\+0x58> 9e ?3e ?44 ?83 ? * cfaddsls mvf4, ?mvf14, ?mvf3
+ 00000584 <fp_arith\+0x5c> de ?32 ?74 ?81 ? * cfaddsle mvf7, ?mvf2, ?mvf1
+ 00000588 <fp_arith\+0x60> 6e ?30 ?b4 ?87 ? * cfaddsvs mvf11, ?mvf0, ?mvf7
+ 0000058c <fp_arith\+0x64> ee ?3c ?34 ?aa ? * cfaddd mvd3, ?mvd12, ?mvd10
+ 00000590 <fp_arith\+0x68> 8e ?3d ?f4 ?a6 ? * cfadddhi mvd15, ?mvd13, ?mvd6
+ 00000594 <fp_arith\+0x6c> 4e ?39 ?24 ?a0 ? * cfadddmi mvd2, ?mvd9, ?mvd0
+ 00000598 <fp_arith\+0x70> ee ?39 ?a4 ?a4 ? * cfaddd mvd10, ?mvd9, ?mvd4
+ 0000059c <fp_arith\+0x74> 3e ?3d ?84 ?a7 ? * cfadddcc mvd8, ?mvd13, ?mvd7
+ 000005a0 <fp_arith\+0x78> 1e ?36 ?c4 ?cb ? * cfsubsne mvf12, ?mvf6, ?mvf11
+ 000005a4 <fp_arith\+0x7c> 7e ?3e ?54 ?c3 ? * cfsubsvc mvf5, ?mvf14, ?mvf3
+ 000005a8 <fp_arith\+0x80> ae ?38 ?14 ?cf ? * cfsubsge mvf1, ?mvf8, ?mvf15
+ 000005ac <fp_arith\+0x84> 6e ?34 ?b4 ?c2 ? * cfsubsvs mvf11, ?mvf4, ?mvf2
+ 000005b0 <fp_arith\+0x88> 0e ?3f ?54 ?ca ? * cfsubseq mvf5, ?mvf15, ?mvf10
+ 000005b4 <fp_arith\+0x8c> 4e ?33 ?e4 ?e8 ? * cfsubdmi mvd14, ?mvd3, ?mvd8
+ 000005b8 <fp_arith\+0x90> 7e ?31 ?24 ?ec ? * cfsubdvc mvd2, ?mvd1, ?mvd12
+ 000005bc <fp_arith\+0x94> be ?37 ?04 ?e5 ? * cfsubdlt mvd0, ?mvd7, ?mvd5
+ 000005c0 <fp_arith\+0x98> 3e ?3a ?c4 ?e1 ? * cfsubdcc mvd12, ?mvd10, ?mvd1
+ 000005c4 <fp_arith\+0x9c> ee ?36 ?d4 ?eb ? * cfsubd mvd13, ?mvd6, ?mvd11
+ 000005c8 <fp_arith\+0xa0> 2e ?10 ?94 ?05 ? * cfmulscs mvf9, ?mvf0, ?mvf5
+ 000005cc <fp_arith\+0xa4> ae ?14 ?94 ?0e ? * cfmulsge mvf9, ?mvf4, ?mvf14
+ 000005d0 <fp_arith\+0xa8> 8e ?17 ?d4 ?02 ? * cfmulshi mvf13, ?mvf7, ?mvf2
+ 000005d4 <fp_arith\+0xac> ce ?1b ?64 ?00 ? * cfmulsgt mvf6, ?mvf11, ?mvf0
+ 000005d8 <fp_arith\+0xb0> 5e ?13 ?e4 ?0c ? * cfmulspl mvf14, ?mvf3, ?mvf12
+ 000005dc <fp_arith\+0xb4> 1e ?1f ?84 ?2d ? * cfmuldne mvd8, ?mvd15, ?mvd13
+ 000005e0 <fp_arith\+0xb8> be ?12 ?44 ?29 ? * cfmuldlt mvd4, ?mvd2, ?mvd9
+ 000005e4 <fp_arith\+0xbc> 5e ?1a ?f4 ?29 ? * cfmuldpl mvd15, ?mvd10, ?mvd9
+ 000005e8 <fp_arith\+0xc0> ee ?18 ?34 ?2d ? * cfmuld mvd3, ?mvd8, ?mvd13
+ 000005ec <fp_arith\+0xc4> 2e ?1c ?14 ?26 ? * cfmuldcs mvd1, ?mvd12, ?mvd6
+ # int_arith:
+ 000005f0 <int_arith> 0e ?35 ?75 ?00 ? * cfabs32eq mvfx7, ?mvfx5
+ 000005f4 <int_arith\+0x4> ee ?3c ?35 ?00 ? * cfabs32 mvfx3, ?mvfx12
+ 000005f8 <int_arith\+0x8> ae ?38 ?15 ?00 ? * cfabs32ge mvfx1, ?mvfx8
+ 000005fc <int_arith\+0xc> ee ?36 ?d5 ?00 ? * cfabs32 mvfx13, ?mvfx6
+ 00000600 <int_arith\+0x10> be ?32 ?45 ?00 ? * cfabs32lt mvfx4, ?mvfx2
+ 00000604 <int_arith\+0x14> 9e ?35 ?05 ?20 ? * cfabs64ls mvdx0, ?mvdx5
+ 00000608 <int_arith\+0x18> ee ?39 ?a5 ?20 ? * cfabs64 mvdx10, ?mvdx9
+ 0000060c <int_arith\+0x1c> 4e ?33 ?e5 ?20 ? * cfabs64mi mvdx14, ?mvdx3
+ 00000610 <int_arith\+0x20> 8e ?37 ?d5 ?20 ? * cfabs64hi mvdx13, ?mvdx7
+ 00000614 <int_arith\+0x24> 2e ?3c ?15 ?20 ? * cfabs64cs mvdx1, ?mvdx12
+ 00000618 <int_arith\+0x28> 6e ?30 ?b5 ?40 ? * cfneg32vs mvfx11, ?mvfx0
+ 0000061c <int_arith\+0x2c> 7e ?3e ?55 ?40 ? * cfneg32vc mvfx5, ?mvfx14
+ 00000620 <int_arith\+0x30> 3e ?3a ?c5 ?40 ? * cfneg32cc mvfx12, ?mvfx10
+ 00000624 <int_arith\+0x34> 1e ?3f ?85 ?40 ? * cfneg32ne mvfx8, ?mvfx15
+ 00000628 <int_arith\+0x38> de ?3b ?65 ?40 ? * cfneg32le mvfx6, ?mvfx11
+ 0000062c <int_arith\+0x3c> 4e ?39 ?25 ?60 ? * cfneg64mi mvdx2, ?mvdx9
+ 00000630 <int_arith\+0x40> 0e ?3f ?55 ?60 ? * cfneg64eq mvdx5, ?mvdx15
+ 00000634 <int_arith\+0x44> ae ?34 ?95 ?60 ? * cfneg64ge mvdx9, ?mvdx4
+ 00000638 <int_arith\+0x48> ee ?38 ?35 ?60 ? * cfneg64 mvdx3, ?mvdx8
+ 0000063c <int_arith\+0x4c> de ?32 ?75 ?60 ? * cfneg64le mvdx7, ?mvdx2
+ 00000640 <int_arith\+0x50> 1e ?36 ?c5 ?8b ? * cfadd32ne mvfx12, ?mvfx6, ?mvfx11
+ 00000644 <int_arith\+0x54> 7e ?3e ?55 ?83 ? * cfadd32vc mvfx5, ?mvfx14, ?mvfx3
+ 00000648 <int_arith\+0x58> ae ?38 ?15 ?8f ? * cfadd32ge mvfx1, ?mvfx8, ?mvfx15
+ 0000064c <int_arith\+0x5c> 6e ?34 ?b5 ?82 ? * cfadd32vs mvfx11, ?mvfx4, ?mvfx2
+ 00000650 <int_arith\+0x60> 0e ?3f ?55 ?8a ? * cfadd32eq mvfx5, ?mvfx15, ?mvfx10
+ 00000654 <int_arith\+0x64> 4e ?33 ?e5 ?a8 ? * cfadd64mi mvdx14, ?mvdx3, ?mvdx8
+ 00000658 <int_arith\+0x68> 7e ?31 ?25 ?ac ? * cfadd64vc mvdx2, ?mvdx1, ?mvdx12
+ 0000065c <int_arith\+0x6c> be ?37 ?05 ?a5 ? * cfadd64lt mvdx0, ?mvdx7, ?mvdx5
+ 00000660 <int_arith\+0x70> 3e ?3a ?c5 ?a1 ? * cfadd64cc mvdx12, ?mvdx10, ?mvdx1
+ 00000664 <int_arith\+0x74> ee ?36 ?d5 ?ab ? * cfadd64 mvdx13, ?mvdx6, ?mvdx11
+ 00000668 <int_arith\+0x78> 2e ?30 ?95 ?c5 ? * cfsub32cs mvfx9, ?mvfx0, ?mvfx5
+ 0000066c <int_arith\+0x7c> ae ?34 ?95 ?ce ? * cfsub32ge mvfx9, ?mvfx4, ?mvfx14
+ 00000670 <int_arith\+0x80> 8e ?37 ?d5 ?c2 ? * cfsub32hi mvfx13, ?mvfx7, ?mvfx2
+ 00000674 <int_arith\+0x84> ce ?3b ?65 ?c0 ? * cfsub32gt mvfx6, ?mvfx11, ?mvfx0
+ 00000678 <int_arith\+0x88> 5e ?33 ?e5 ?cc ? * cfsub32pl mvfx14, ?mvfx3, ?mvfx12
+ 0000067c <int_arith\+0x8c> 1e ?3f ?85 ?ed ? * cfsub64ne mvdx8, ?mvdx15, ?mvdx13
+ 00000680 <int_arith\+0x90> be ?32 ?45 ?e9 ? * cfsub64lt mvdx4, ?mvdx2, ?mvdx9
+ 00000684 <int_arith\+0x94> 5e ?3a ?f5 ?e9 ? * cfsub64pl mvdx15, ?mvdx10, ?mvdx9
+ 00000688 <int_arith\+0x98> ee ?38 ?35 ?ed ? * cfsub64 mvdx3, ?mvdx8, ?mvdx13
+ 0000068c <int_arith\+0x9c> 2e ?3c ?15 ?e6 ? * cfsub64cs mvdx1, ?mvdx12, ?mvdx6
+ 00000690 <int_arith\+0xa0> 0e ?15 ?75 ?0e ? * cfmul32eq mvfx7, ?mvfx5, ?mvfx14
+ 00000694 <int_arith\+0xa4> ce ?11 ?a5 ?08 ? * cfmul32gt mvfx10, ?mvfx1, ?mvfx8
+ 00000698 <int_arith\+0xa8> de ?1b ?65 ?04 ? * cfmul32le mvfx6, ?mvfx11, ?mvfx4
+ 0000069c <int_arith\+0xac> 9e ?15 ?05 ?0f ? * cfmul32ls mvfx0, ?mvfx5, ?mvfx15
+ 000006a0 <int_arith\+0xb0> 9e ?1e ?45 ?03 ? * cfmul32ls mvfx4, ?mvfx14, ?mvfx3
+ 000006a4 <int_arith\+0xb4> de ?12 ?75 ?21 ? * cfmul64le mvdx7, ?mvdx2, ?mvdx1
+ 000006a8 <int_arith\+0xb8> 6e ?10 ?b5 ?27 ? * cfmul64vs mvdx11, ?mvdx0, ?mvdx7
+ 000006ac <int_arith\+0xbc> ee ?1c ?35 ?2a ? * cfmul64 mvdx3, ?mvdx12, ?mvdx10
+ 000006b0 <int_arith\+0xc0> 8e ?1d ?f5 ?26 ? * cfmul64hi mvdx15, ?mvdx13, ?mvdx6
+ 000006b4 <int_arith\+0xc4> 4e ?19 ?25 ?20 ? * cfmul64mi mvdx2, ?mvdx9, ?mvdx0
+ 000006b8 <int_arith\+0xc8> ee ?19 ?a5 ?44 ? * cfmac32 mvfx10, ?mvfx9, ?mvfx4
+ 000006bc <int_arith\+0xcc> 3e ?1d ?85 ?47 ? * cfmac32cc mvfx8, ?mvfx13, ?mvfx7
+ 000006c0 <int_arith\+0xd0> 1e ?16 ?c5 ?4b ? * cfmac32ne mvfx12, ?mvfx6, ?mvfx11
+ 000006c4 <int_arith\+0xd4> 7e ?1e ?55 ?43 ? * cfmac32vc mvfx5, ?mvfx14, ?mvfx3
+ 000006c8 <int_arith\+0xd8> ae ?18 ?15 ?4f ? * cfmac32ge mvfx1, ?mvfx8, ?mvfx15
+ 000006cc <int_arith\+0xdc> 6e ?14 ?b5 ?62 ? * cfmsc32vs mvfx11, ?mvfx4, ?mvfx2
+ 000006d0 <int_arith\+0xe0> 0e ?1f ?55 ?6a ? * cfmsc32eq mvfx5, ?mvfx15, ?mvfx10
+ 000006d4 <int_arith\+0xe4> 4e ?13 ?e5 ?68 ? * cfmsc32mi mvfx14, ?mvfx3, ?mvfx8
+ 000006d8 <int_arith\+0xe8> 7e ?11 ?25 ?6c ? * cfmsc32vc mvfx2, ?mvfx1, ?mvfx12
+ 000006dc <int_arith\+0xec> be ?17 ?05 ?65 ? * cfmsc32lt mvfx0, ?mvfx7, ?mvfx5
+ # acc_arith:
+ 000006e0 <acc_arith> 3e ?01 ?a6 ?08 ? * cfmadd32cc mvax0, ?mvfx10, ?mvfx1, ?mvfx8
+ 000006e4 <acc_arith\+0x4> ee ?0b ?66 ?44 ? * cfmadd32 mvax2, ?mvfx6, ?mvfx11, ?mvfx4
+ 000006e8 <acc_arith\+0x8> 2e ?05 ?06 ?2f ? * cfmadd32cs mvax1, ?mvfx0, ?mvfx5, ?mvfx15
+ 000006ec <acc_arith\+0xc> ae ?0e ?46 ?43 ? * cfmadd32ge mvax2, ?mvfx4, ?mvfx14, ?mvfx3
+ 000006f0 <acc_arith\+0x10> 8e ?02 ?76 ?61 ? * cfmadd32hi mvax3, ?mvfx7, ?mvfx2, ?mvfx1
+ 000006f4 <acc_arith\+0x14> ce ?10 ?b6 ?07 ? * cfmsub32gt mvax0, ?mvfx11, ?mvfx0, ?mvfx7
+ 000006f8 <acc_arith\+0x18> 5e ?1c ?36 ?4a ? * cfmsub32pl mvax2, ?mvfx3, ?mvfx12, ?mvfx10
+ 000006fc <acc_arith\+0x1c> 1e ?1d ?f6 ?26 ? * cfmsub32ne mvax1, ?mvfx15, ?mvfx13, ?mvfx6
+ 00000700 <acc_arith\+0x20> be ?19 ?26 ?40 ? * cfmsub32lt mvax2, ?mvfx2, ?mvfx9, ?mvfx0
+ 00000704 <acc_arith\+0x24> 5e ?19 ?a6 ?64 ? * cfmsub32pl mvax3, ?mvfx10, ?mvfx9, ?mvfx4
+ 00000708 <acc_arith\+0x28> ee ?2d ?16 ?67 ? * cfmadda32 mvax3, ?mvax1, ?mvfx13, ?mvfx7
+ 0000070c <acc_arith\+0x2c> 2e ?26 ?26 ?6b ? * cfmadda32cs mvax3, ?mvax2, ?mvfx6, ?mvfx11
+ 00000710 <acc_arith\+0x30> 0e ?2e ?36 ?23 ? * cfmadda32eq mvax1, ?mvax3, ?mvfx14, ?mvfx3
+ 00000714 <acc_arith\+0x34> ce ?28 ?36 ?2f ? * cfmadda32gt mvax1, ?mvax3, ?mvfx8, ?mvfx15
+ 00000718 <acc_arith\+0x38> de ?24 ?36 ?02 ? * cfmadda32le mvax0, ?mvax3, ?mvfx4, ?mvfx2
+ 0000071c <acc_arith\+0x3c> 9e ?3f ?16 ?0a ? * cfmsuba32ls mvax0, ?mvax1, ?mvfx15, ?mvfx10
+ 00000720 <acc_arith\+0x40> 9e ?33 ?16 ?08 ? * cfmsuba32ls mvax0, ?mvax1, ?mvfx3, ?mvfx8
+ 00000724 <acc_arith\+0x44> de ?31 ?06 ?4c ? * cfmsuba32le mvax2, ?mvax0, ?mvfx1, ?mvfx12
+ 00000728 <acc_arith\+0x48> 6e ?37 ?06 ?25 ? * cfmsuba32vs mvax1, ?mvax0, ?mvfx7, ?mvfx5
+ 0000072c <acc_arith\+0x4c> ee ?3a ?06 ?41 ? * cfmsuba32 mvax2, ?mvax0, ?mvfx10, ?mvfx1