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Re: ELF for PPC32


> From: Torbjorn Granlund <tege@swox.com>
> Date: 12 Mar 2001 23:57:34 +0100

> While working on implementing the 64-bit ELF ABI for PowerPC, we
> obsevered a discrepancy between the 64-bit ABI and how the 32-bit ABI
> is actually implemented in gas/config/tc-ppc.c and in bfd/elf32-ppc.c.
> 
> The discrepancy is in the relocation address of R_PPC_ADDR14,
> R_PPC_REL14.  The 64-bit ABI states:
> 
>   Relocation entries apply to halfwords, words, or doublewords.  In
>   all cases, the r_offset value designates the offset or virtual
>   address of the first byte of the affected storage unit.
> 
> The current 32-bit implementation doesn't do like that for
> R_PPC_ADDR14 and R_PPC_REL14.  It uses the address of the first byte
> of the instruction, which isn't the same thing (except for under
> little-endian mode).

The ABI says that the R_PPC_ADDR14 and R_PPC_REL14 relocs refer to a
field of type 'low14', which is: `This specifies a 14-bit field
contained within a word with 4-byte alignment, comprising a
conditional branch instruction.  The 14-bit relative displacement in
bits 16-29, and possibly the "branch prediction bit" (bit 10) are
altered; all other bits remain unchanged.'

I think that for R_PPC_ADDR14 and R_PPC_REL14, the branch prediction
bit is not in fact altered, but it is altered for R_PPC_ADDR14_BRTAKEN
and so on.  I believe the linker is free to change the branch
prediction bit if it thinks it would help (for instance, a linker
which has profiling data available to it).

I think it's likely that the 64-bit ABI intended the relocation to
apply to a 4-byte word, in which case there'd be no inconsistency.

-- 
- Geoffrey Keating <geoffk@geoffk.org>


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