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[Pactch] ARM sim fix for ORR and STRD
- To: binutils at sources dot redhat dot com
- Subject: [Pactch] ARM sim fix for ORR and STRD
- From: Nick Clifton <nickc at redhat dot com>
- Date: Mon, 18 Dec 2000 17:01:38 -0800
Hi Guys,
I have just checked in the patch below to fix the decoding of the
STRD instruction which was accidentally colliding with the decoding
of the ORR instruction.
Cheers
Nick
2000-12-18 Nick Clifton <nickc@redhat.com>
* armemu.c (ARMul_Emulate26): Fix test for StoreDouble
instruction.
Index: sim/arm/armemu.c
===================================================================
RCS file: /cvs/cvsfiles/devo/sim/arm/armemu.c,v
retrieving revision 1.17.2.29.2.5
diff -p -r1.17.2.29.2.5 armemu.c
*** armemu.c 2000/12/14 23:59:40 1.17.2.29.2.5
--- armemu.c 2000/12/19 00:46:08
*************** ARMul_Emulate26 (register ARMul_State *
*** 612,618 ****
Handle_Load_Double (state, instr);
break;
}
! if (BITS (4, 7) == 0xE)
{
Handle_Store_Double (state, instr);
break;
--- 612,618 ----
Handle_Load_Double (state, instr);
break;
}
! if (BITS (4, 7) == 0xF)
{
Handle_Store_Double (state, instr);
break;
*************** ARMul_Emulate26 (register ARMul_State *
*** 780,786 ****
Handle_Load_Double (state, instr);
break;
}
! if (BITS (4, 7) == 0xE)
{
Handle_Store_Double (state, instr);
break;
--- 780,786 ----
Handle_Load_Double (state, instr);
break;
}
! if (BITS (4, 7) == 0xF)
{
Handle_Store_Double (state, instr);
break;
*************** ARMul_Emulate26 (register ARMul_State *
*** 868,874 ****
Handle_Load_Double (state, instr);
break;
}
! if (BITS (4, 7) == 0xE)
{
Handle_Store_Double (state, instr);
break;
--- 868,874 ----
Handle_Load_Double (state, instr);
break;
}
! if (BITS (4, 7) == 0xF)
{
Handle_Store_Double (state, instr);
break;
*************** ARMul_Emulate26 (register ARMul_State *
*** 1002,1008 ****
Handle_Load_Double (state, instr);
break;
}
! if (BITS (4, 7) == 0xE)
{
Handle_Store_Double (state, instr);
break;
--- 1002,1008 ----
Handle_Load_Double (state, instr);
break;
}
! if (BITS (4, 7) == 0xF)
{
Handle_Store_Double (state, instr);
break;
*************** ARMul_Emulate26 (register ARMul_State *
*** 1167,1173 ****
Handle_Load_Double (state, instr);
break;
}
! if (BITS (4, 7) == 0xE)
{
Handle_Store_Double (state, instr);
break;
--- 1167,1173 ----
Handle_Load_Double (state, instr);
break;
}
! if (BITS (4, 7) == 0xF)
{
Handle_Store_Double (state, instr);
break;
*************** ARMul_Emulate26 (register ARMul_State *
*** 1308,1314 ****
Handle_Load_Double (state, instr);
break;
}
! if (BITS (4, 7) == 0xE)
{
Handle_Store_Double (state, instr);
break;
--- 1308,1314 ----
Handle_Load_Double (state, instr);
break;
}
! if (BITS (4, 7) == 0xF)
{
Handle_Store_Double (state, instr);
break;
*************** ARMul_Emulate26 (register ARMul_State *
*** 1470,1476 ****
Handle_Load_Double (state, instr);
break;
}
! if (BITS (4, 7) == 0xE)
{
Handle_Store_Double (state, instr);
break;
--- 1470,1476 ----
Handle_Load_Double (state, instr);
break;
}
! if (BITS (4, 7) == 0xF)
{
Handle_Store_Double (state, instr);
break;
*************** ARMul_Emulate26 (register ARMul_State *
*** 1617,1623 ****
Handle_Load_Double (state, instr);
break;
}
! if (BITS (4, 7) == 0xE)
{
Handle_Store_Double (state, instr);
break;
--- 1617,1623 ----
Handle_Load_Double (state, instr);
break;
}
! if (BITS (4, 7) == 0xF)
{
Handle_Store_Double (state, instr);
break;
*************** ARMul_Emulate26 (register ARMul_State *
*** 1689,1695 ****
Handle_Load_Double (state, instr);
break;
}
! if (BITS (4, 7) == 0xE)
{
Handle_Store_Double (state, instr);
break;
--- 1689,1695 ----
Handle_Load_Double (state, instr);
break;
}
! if (BITS (4, 7) == 0xF)
{
Handle_Store_Double (state, instr);
break;
*************** ARMul_Emulate26 (register ARMul_State *
*** 1727,1733 ****
Handle_Load_Double (state, instr);
break;
}
! if (BITS (4, 7) == 0xE)
{
Handle_Store_Double (state, instr);
break;
--- 1727,1733 ----
Handle_Load_Double (state, instr);
break;
}
! if (BITS (4, 7) == 0xF)
{
Handle_Store_Double (state, instr);
break;
*************** ARMul_Emulate26 (register ARMul_State *
*** 1763,1769 ****
Handle_Load_Double (state, instr);
break;
}
! else if (BITS (4, 7) == 0xE)
{
Handle_Store_Double (state, instr);
break;
--- 1763,1769 ----
Handle_Load_Double (state, instr);
break;
}
! else if (BITS (4, 7) == 0xF)
{
Handle_Store_Double (state, instr);
break;
*************** ARMul_Emulate26 (register ARMul_State *
*** 1801,1807 ****
Handle_Load_Double (state, instr);
break;
}
! if (BITS (4, 7) == 0xE)
{
Handle_Store_Double (state, instr);
break;
--- 1801,1807 ----
Handle_Load_Double (state, instr);
break;
}
! if (BITS (4, 7) == 0xF)
{
Handle_Store_Double (state, instr);
break;