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Patch H8300/S Bit instruction Relaxing


Here are patches to the CVS binutils to extend relaxation on h8300 target to
include bit operation instructions. The H8S bit operations include
addressing modes @:32 @:16 and @:8
These patches relax both @:32 and @:16 bitops to more efficient modes.

Paul Clarke



Changelog Entry
bfd/coff-h8300.c

Change the message on the mov.b relocation so that it is applicable to 
H8 bit operations as well.

Change the mov.b relax method so that it will handle bit opcodes.

Fix the 16 bit reloc so that it will abort if the relax addresses are not 
in the 16 bit area.


*** coff-h8300.c	Thu May 25 09:40:35 2000
--- coff-h8300.c.new	Thu May 25 09:44:16 2000
***************
*** 226,233 ****
    HOWTO (R_PCRBYTE, 0, 0, 8, true, 0, complain_overflow_signed, special,
"DISP8", false, 0x000000ff, 0x000000ff, true),
    HOWTO (R_PCRWORD, 0, 1, 16, true, 0, complain_overflow_signed, special,
"DISP16", false, 0x0000ffff, 0x0000ffff, true),
    HOWTO (R_PCRLONG, 0, 2, 32, true, 0, complain_overflow_signed, special,
"DISP32", false, 0xffffffff, 0xffffffff, true),
!   HOWTO (R_MOV16B1, 0, 1, 16, false, 0, complain_overflow_bitfield,
special, "relaxable mov.b:16", false, 0x0000ffff, 0x0000ffff, false),
!   HOWTO (R_MOV16B2, 0, 1, 8, false, 0, complain_overflow_bitfield,
special, "relaxed mov.b:16", false, 0x000000ff, 0x000000ff, false),
    HOWTO (R_JMP1, 0, 1, 16, false, 0, complain_overflow_bitfield, special,
"16/pcrel", false, 0x0000ffff, 0x0000ffff, false),
    HOWTO (R_JMP2, 0, 0, 8, false, 0, complain_overflow_bitfield, special,
"pcrecl/16", false, 0x000000ff, 0x000000ff, false),
    HOWTO (R_JMPL1, 0, 2, 32, false, 0, complain_overflow_bitfield, special,
"24/pcrell", false, 0x00ffffff, 0x00ffffff, false),
--- 226,233 ----
    HOWTO (R_PCRBYTE, 0, 0, 8, true, 0, complain_overflow_signed, special,
"DISP8", false, 0x000000ff, 0x000000ff, true),
    HOWTO (R_PCRWORD, 0, 1, 16, true, 0, complain_overflow_signed, special,
"DISP16", false, 0x0000ffff, 0x0000ffff, true),
    HOWTO (R_PCRLONG, 0, 2, 32, true, 0, complain_overflow_signed, special,
"DISP32", false, 0xffffffff, 0xffffffff, true),
!   HOWTO (R_MOV16B1, 0, 1, 16, false, 0, complain_overflow_bitfield,
special, "relaxable bitop|mov.b:16", false, 0x0000ffff, 0x0000ffff, false),
!   HOWTO (R_MOV16B2, 0, 1, 8, false, 0, complain_overflow_bitfield,
special, "relaxed bitop|mov.b:16", false, 0x000000ff, 0x000000ff, false),
    HOWTO (R_JMP1, 0, 1, 16, false, 0, complain_overflow_bitfield, special,
"16/pcrel", false, 0x0000ffff, 0x0000ffff, false),
    HOWTO (R_JMP2, 0, 0, 8, false, 0, complain_overflow_bitfield, special,
"pcrecl/16", false, 0x000000ff, 0x000000ff, false),
    HOWTO (R_JMPL1, 0, 2, 32, false, 0, complain_overflow_bitfield, special,
"24/pcrell", false, 0x00ffffff, 0x00ffffff, false),
***************
*** 762,770 ****
      case R_JMP1:
      case R_RELWORD:
        value = bfd_coff_reloc16_get_value(reloc, link_info, input_section);
!       bfd_put_16 (abfd, value, data + dst_address);
        dst_address += 2;
        src_address += 2;
        break;
  
      /* Various simple 24/32bit absolute relocations.  */
--- 762,785 ----
      case R_JMP1:
      case R_RELWORD:
        value = bfd_coff_reloc16_get_value(reloc, link_info, input_section);
!       if (value <= 0x7fff
!   	  || (value >= 0x00ff8000 && value <= 0x00ffffff))
! 	{
! 	  /* Everything looks OK.  Apply the relocation and update the
! 	     src/dst address appropriately.  */
! 
! 	  bfd_put_16 (abfd, value & 0xffff, data + dst_address);
  	  dst_address += 2;
  	  src_address += 2;
+ 	}
+       else
+ 	{
+ 	  if (! ((*link_info->callbacks->reloc_overflow)
+ 		 (link_info, bfd_asymbol_name (*reloc->sym_ptr_ptr),
+ 		  reloc->howto->name, reloc->addend, input_section->owner,
+ 		  input_section, reloc->address)))
+ 	    abort ();
+ 	}
        break;
  
      /* Various simple 24/32bit absolute relocations.  */
***************
*** 969,974 ****
--- 984,992 ----
  	case 0x80:
  	  data[dst_address - 2] = (data[src_address-1] & 0xf) | 0x30;
  	  break;
+ 	case 0x10:
+ 	  data[dst_address - 2] = (data[dst_address-1] & 0x08) ? 0x7f :
0x7e;
+ 	  break;
  	default:
  	  abort ();
  	}
***************
*** 993,998 ****
--- 1011,1019 ----
  	  break;
  	case 0xa0:
  	  data[dst_address - 2] = (data[src_address-1] & 0xf) | 0x30;
+ 	  break;
+ 	case 0x30:
+ 	  data[dst_address - 2] = (data[dst_address-1] & 0x08) ? 0x7f :
0x7e;
  	  break;
  	default:
  	  abort ();

gas/config/tc-h8300.c

Test for h8300 bit instructions. The H8S can relax them from @:32 to @:16 or
@:8

*** tc-h8300.c	Thu May 25 09:40:35 2000
--- tc-h8300.c.new	Thu May 25 09:45:09 2000
***************
*** 959,971 ****
    int immat;
    int nib;
    int movb = 0;
    char asnibbles[30];
    char *p = asnibbles;
  
    if (!(this_try->inbase || Hmode))
      as_warn (_("Opcode `%s' with these operand types not available in
H8/300 mode"),
  	     this_try->name);
! 
    while (*nibble_ptr != E)
      {
        int d;
--- 959,973 ----
    int immat;
    int nib;
    int movb = 0;
+   int bitop = 0;
    char asnibbles[30];
    char *p = asnibbles;
  
    if (!(this_try->inbase || Hmode))
+     {
      as_warn (_("Opcode `%s' with these operand types not available in
H8/300 mode"),
  	     this_try->name);
!     }
    while (*nibble_ptr != E)
      {
        int d;
***************
*** 1085,1090 ****
--- 1087,1110 ----
    if (strcmp (this_try->name, "mov.b") == 0)
      movb = 1;
  
+   /* if this is a bit instruction -- there's a special relaxation
+      which only applies to them.  */
+   if (Smode && ((strcmp (this_try->name, "bset") == 0)
+       ||(strcmp (this_try->name, "bclr") == 0)
+       ||(strcmp (this_try->name, "bnot") == 0)
+       ||(strcmp (this_try->name, "btst") == 0)
+       ||(strcmp (this_try->name, "bld") == 0)
+       ||(strcmp (this_try->name, "bild") == 0)
+       ||(strcmp (this_try->name, "bst") == 0)
+       ||(strcmp (this_try->name, "bist") == 0)
+       ||(strcmp (this_try->name, "band") == 0)
+       ||(strcmp (this_try->name, "biand") == 0)
+       ||(strcmp (this_try->name, "bor") == 0)
+       ||(strcmp (this_try->name, "bior") == 0)
+       ||(strcmp (this_try->name, "bxor") == 0)
+       ||(strcmp (this_try->name, "bixor") == 0)))
+     bitop = 1;
+ 
    /* output any fixes */
    for (i = 0; i < 2; i++)
      {
***************
*** 1097,1104 ****
--- 1117,1132 ----
  	}
        else if (x & ABS)
  	{
+ 	  if (bitop)
+ 	    {
+ 	       do_a_fix_imm (output - frag_now->fr_literal + absat,
+ 			operand + i, x & MEMRELAX ? 2 : 0);
+ 	    }
+ 	  else
+ 	    {
  	      do_a_fix_imm (output - frag_now->fr_literal + absat,
  			operand + i, x & MEMRELAX ? movb + 1 : 0);
+ 	    }
  	}
        else if (x & PCREL)
  	{


include/opcode/h8300.h

Add MEMRELAX capability to the bit operation opcodes.

*** h8300.h	Thu May 25 09:40:35 2000
--- h8300.h.new	Thu May 25 09:48:19 2000
***************
*** 162,169 ****
  { code, 1, 2, name,	{{imm,RD8,E}},	{{op00, op01, imm, RD8, E, 0, 0, 0,
0}}, 0, 0, 0, 0},\
  { code, 1, 6, name,	{{imm,RDIND,E}},{{op10, op11, B30|RDIND, 0,
op00,op01, imm, 0, E}}, 0, 0, 0, 0},\
  { code, 1, 6, name,	{{imm,ABS8DST,E}},{{op20, op21, ABS8DST, IGNORE,
op00,op01, imm, 0,E}}, 0, 0, 0, 0}\
! ,{ code, 0, 6, name,
{{imm,ABS16DST,E}},{{0x6,0xa,0x1,op30,ABS16DST,IGNORE,IGNORE,IGNORE,
op00,op01, imm, 0,E}}, 0, 0, 0, 0},\
! { code, 0, 6, name,
{{imm,ABS32DST,E}},{{0x6,0xa,0x3,op30,ABS32DST,IGNORE,IGNORE,IGNORE,IGNORE,I
GNORE,IGNORE,IGNORE, op00,op01, imm, 0,E}}, 0, 0, 0, 0}
  
  
  #define EBITOP(code, imm, name, op00, op01,op10,op11, op20,op21,op30)\
--- 162,169 ----
  { code, 1, 2, name,	{{imm,RD8,E}},	{{op00, op01, imm, RD8, E, 0, 0, 0,
0}}, 0, 0, 0, 0},\
  { code, 1, 6, name,	{{imm,RDIND,E}},{{op10, op11, B30|RDIND, 0,
op00,op01, imm, 0, E}}, 0, 0, 0, 0},\
  { code, 1, 6, name,	{{imm,ABS8DST,E}},{{op20, op21, ABS8DST, IGNORE,
op00,op01, imm, 0,E}}, 0, 0, 0, 0}\
! ,{ code, 0, 6, name,
{{imm,ABS16DST,E}},{{0x6,0xa,0x1,op30,ABS16DST|MEMRELAX,IGNORE,IGNORE,IGNORE
, op00,op01, imm, 0,E}}, 0, 0, 0, 0},\
! { code, 0, 6, name,
{{imm,ABS32DST,E}},{{0x6,0xa,0x3,op30,ABS32DST|MEMRELAX,IGNORE,IGNORE,IGNORE
,IGNORE,IGNORE,IGNORE,IGNORE, op00,op01, imm, 0,E}}, 0, 0, 0, 0}
  
  
  #define EBITOP(code, imm, name, op00, op01,op10,op11, op20,op21,op30)\



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