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patch for include/opcode: PowerPC vector unit support
- To: binutils at sourceware dot cygnus dot com
- Subject: patch for include/opcode: PowerPC vector unit support
- From: jtc at redback dot com (J.T. Conklin)
- Date: 02 May 2000 11:17:42 -0700
- Reply-To: jtc at redback dot com
2000-05-02 J.T. Conklin <jtc@redback.com>
* ppc.h (PPC_OPCODE_ALTIVEC): New opcode flag for vector unit.
(PPC_OPERAND_VR): New operand flag for vector registers.
Index: ppc.h
===================================================================
RCS file: /cvs/src/src/include/opcode/ppc.h,v
retrieving revision 1.2
diff -c -r1.2 ppc.h
*** ppc.h 1999/05/08 23:28:34 1.2
--- ppc.h 2000/05/02 17:46:45
***************
*** 88,93 ****
--- 88,96 ----
/* Opcode is supported as part of the 64-bit bridge. */
#define PPC_OPCODE_64_BRIDGE (0400)
+ /* Opcode is supported by Altivec Vector Unit */
+ #define PPC_OPCODE_ALTIVEC (01000)
+
/* A macro to extract the major opcode from an instruction. */
#define PPC_OP(i) (((i) >> 26) & 0x3f)
***************
*** 221,226 ****
--- 224,234 ----
number is allowed). This flag will only be set for a signed
operand. */
#define PPC_OPERAND_NEGATIVE (04000)
+
+ /* This operand names a vector unit register. The disassembler
+ prints these with a leading 'v'. */
+ #define PPC_OPERAND_VR (010000)
+
/* The POWER and PowerPC assemblers use a few macros. We keep them
with the operands table for simplicity. The macro table is an
--
J.T. Conklin
RedBack Networks